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| Presentation | 2009-12-04 10:40 Transistor-Array-Based Opamp Layout and its Evaluationon Arisa Kawazoe, Toru Fujimura, Shigetoshi Nakatake (Univ. of Kitakyushu)  VLD2009-60 DC2009-47 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper proposes a novel MOS analog design style along with layout automation, called Transistor-Array (TA), which makes use of regular bulk structures. For typical OPAMP circuits, we laid out them in the custom layout style and the TA layout style, and compared the resultant with respect to the area. As well, we implemented the circuit into the TEG and measured their offset voltages to check the influences by the process variation. Analyzing these results, it is convinced that a design automation based on TA layout style is promising to generate layouts with sufficient circuit quality as well as area utilization. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Transistor-Array / Analog Layout / OPAMP / Offset Voltage / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 315, VLD2009-60, pp. 131-136, Dec. 2009. | |
| Paper # | VLD2009-60 | |
| Date of Issue | 2009-11-25 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-60 DC2009-47 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2009-12-02 - 2009-12-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi City Culture-Plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2009 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Transistor-Array-Based Opamp Layout and its Evaluationon |
| Sub Title (in English) | |
| Keyword(1) | Transistor-Array |
| Keyword(2) | Analog Layout |
| Keyword(3) | OPAMP |
| Keyword(4) | Offset Voltage |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Arisa Kawazoe |
| 1st Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
| 2nd Author's Name | Toru Fujimura |
| 2nd Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
| 3rd Author's Name | Shigetoshi Nakatake |
| 3rd Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
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| Speaker | Author-1 |
| Date Time | 2009-12-04 10:40:00 |
| Presentation Time | 20 minutes |
| Registration for | VLD |
| Paper # | VLD2009-60, DC2009-47 |
| Volume (vol) | vol.109 |
| Number (no) | no.315(VLD), no.316(DC) |
| Page | pp.131-136 |
| #Pages | 6 |
| Date of Issue | 2009-11-25 (VLD, DC) |
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