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Paper Abstract and Keywords
Presentation 2010-01-15 11:45
Cost Effective Wafer-Level Chip Size Package Technology and Application for High Speed Wireless Communications.
Seiji Fujita, Masaki Imagawa, Tomio Satoh (SEDI), Tsuneo Tokumitsu (SEI), Yuichi Hasegawa (SEDI) ED2009-195 MW2009-178 Link to ES Tech. Rep. Archives: ED2009-195 MW2009-178
Abstract (in Japanese) (See Japanese page) 
(in English) Cost effective Ku-band up-mixer and down-mixer MMIC’s, that use a three-dimensional MMIC technology optimized for flip-chip implementation, are presented. The MMIC structure incorporates inverse TFMS lines so that a ground metal can be applied to cover the whole chip surface except for interconnect pads. Among multi polyimide and SiN layers, four wiring metal layers are composed. Hence, these MMIC chips require no package, as well as can be directly assembled on PC board. The up-mixer MMIC is composed of a pair of balanced mixers, which are doubly balanced with additional quadrature couplers, and a LO amplifier. The down-mixer is composed of an image-rejection mixer, a LO amplifier and a low-noise amplifier with a noise figure of 3.2 dB. The amplifiers are very linear and provide an OIP3 of nearly 25dBm.
The up-mixer exhibits a conversion loss of the 12dB, the IMD ratios of nearly -55dBc at -5dBm 2-tone IF input. The LO-to-RF leakage suppression is as well as -30dBc. The down-mixer exhibits a conversion gain of 6.5dB, a noise figure of nearly 3.7dB, and an IIP3 of 0dBm to 5dBm between 12GHz and 16GHz. The die size of them is 2.4mm x 2.4mm and consumes 36mA and 72mA, respectively, fed from 5V power supply.
Keyword (in Japanese) (See Japanese page) 
(in English) WLCSP / three-dimensional / wireless communications / up-converter / down-converter / flipchip / mixer /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 361, MW2009-178, pp. 117-121, Jan. 2010.
Paper # MW2009-178 
Date of Issue 2010-01-06 (ED, MW) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ED2009-195 MW2009-178 Link to ES Tech. Rep. Archives: ED2009-195 MW2009-178

Conference Information
Committee ED MW  
Conference Date 2010-01-13 - 2010-01-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To MW 
Conference Code 2010-01-ED-MW 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Cost Effective Wafer-Level Chip Size Package Technology and Application for High Speed Wireless Communications. 
Sub Title (in English)  
Keyword(1) WLCSP  
Keyword(2) three-dimensional  
Keyword(3) wireless communications  
Keyword(4) up-converter  
Keyword(5) down-converter  
Keyword(6) flipchip  
Keyword(7) mixer  
Keyword(8)  
1st Author's Name Seiji Fujita  
1st Author's Affiliation Sumitomo Electric Device Innovations INC (SEDI)
2nd Author's Name Masaki Imagawa  
2nd Author's Affiliation Sumitomo Electric Device Innovations INC (SEDI)
3rd Author's Name Tomio Satoh  
3rd Author's Affiliation Sumitomo Electric Device Innovations INC (SEDI)
4th Author's Name Tsuneo Tokumitsu  
4th Author's Affiliation Sumitomo Electric Industries, Ltd (SEI)
5th Author's Name Yuichi Hasegawa  
5th Author's Affiliation Sumitomo Electric Device Innovations INC (SEDI)
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Speaker Author-1 
Date Time 2010-01-15 11:45:00 
Presentation Time 25 minutes 
Registration for MW 
Paper # ED2009-195, MW2009-178 
Volume (vol) vol.109 
Number (no) no.360(ED), no.361(MW) 
Page pp.117-121 
#Pages
Date of Issue 2010-01-06 (ED, MW) 


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