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Paper Abstract and Keywords
Presentation 2010-01-26 17:10
A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching
Norihiro Hashimoto, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-83 CPSY2009-65 RECONF2009-68
Abstract (in Japanese) (See Japanese page) 
(in English) Requirement for application-specific processor is really increasing recently, however, it takes much time to design a processor for each application.Therefore, we require an automatic synthesis system for application-specific processors.In this paper, we propose a dedicated functional unit syntesis algorithm for an application-specific processor.
Our algorithm synthesizes a dedicated funcitonal unit with MISO (Multiple Input, Single Output) structure.Additionally, our algorithm performs partial matching, which makes a dedicated unit execute fuctions even if a dedicated unit corresponds to a subgraph of CDFG (Control-Data Flow Graph) partially.It is realized by making unnecessary functions execute with 0 or 1 as an input.Our algorithm acheived 52\% of time reduction compared to previous approaches.
Keyword (in Japanese) (See Japanese page) 
(in English) Custom Instruction / CDFG / MISO / Partial Matching / Hardware/Software Partitioning / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 393, VLD2009-83, pp. 89-94, Jan. 2010.
Paper # VLD2009-83 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-83 CPSY2009-65 RECONF2009-68

Conference Information
Conference Date 2010-01-26 - 2010-01-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2010-01-SLDM-VLD-CPSY-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching 
Sub Title (in English)  
Keyword(1) Custom Instruction  
Keyword(2) CDFG  
Keyword(3) MISO  
Keyword(4) Partial Matching  
Keyword(5) Hardware/Software Partitioning  
1st Author's Name Norihiro Hashimoto  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Nozomu Togawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Tatsuo Ohtsuki  
4th Author's Affiliation Waseda University (Waseda Univ.)
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Date Time 2010-01-26 17:10:00 
Presentation Time 25 
Registration for VLD 
Paper # VLD2009-83, CPSY2009-65, RECONF2009-68 
Volume (vol) 109 
Number (no) no.393(VLD), no.394(CPSY), no.395(RECONF) 
Page pp.89-94 
Date of Issue 2010-01-19 (VLD, CPSY, RECONF) 

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