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| Presentation | 2010-01-26 13:30 An FPGA Implementation of Array Processor Performing 3D-DCT Effectively Yuki Ikegaki, Hiroyuki Igarashi, Toshiaki Miyazaki, Stanislav G. Sedukhin (Univ. of Aizu)  VLD2009-76 CPSY2009-58 RECONF2009-61 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Ordinary array processors randomly access to input-/coefficient-data in external memories many times during the 3D-DCT, and it is a significant bottleneck of the high-speed data processing. In this paper, three dimensional array processor dedicated to 3D-DCT is proposed. The array processor extremely reduces the data swapping or replacement during calculation, and it contributes to improving the performance greatly. The computational complexity of the proposed array processor is O(N) for an N×N×N input data cube, while that of the 3D-DCT direct calculation is O(N^4). Data I/O and area-improved architectures are also discussed in consideration of their practical implementation. The proposed array processor is implemented in an FPGA. The FPGA implementation results show that our architecture satisfies performance for real-time 3D-DCT with rich scalability. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | 3D-DCT / 3D-LSI / Array processor / FPGA implementation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 395, RECONF2009-61, pp. 41-46, Jan. 2010. | |
| Paper # | RECONF2009-61 | |
| Date of Issue | 2010-01-19 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-76 CPSY2009-58 RECONF2009-61 |
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| Conference Information | |
| Committee | IPSJ-SLDM VLD CPSY RECONF |
| Conference Date | 2010-01-26 - 2010-01-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Keio Univ (Hiyoshi Campus) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2010-01-SLDM-VLD-CPSY-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA Implementation of Array Processor Performing 3D-DCT Effectively |
| Sub Title (in English) | |
| Keyword(1) | 3D-DCT |
| Keyword(2) | 3D-LSI |
| Keyword(3) | Array processor |
| Keyword(4) | FPGA implementation |
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| 1st Author's Name | Yuki Ikegaki |
| 1st Author's Affiliation | The University of Aizu (Univ. of Aizu) |
| 2nd Author's Name | Hiroyuki Igarashi |
| 2nd Author's Affiliation | The University of Aizu (Univ. of Aizu) |
| 3rd Author's Name | Toshiaki Miyazaki |
| 3rd Author's Affiliation | The University of Aizu (Univ. of Aizu) |
| 4th Author's Name | Stanislav G. Sedukhin |
| 4th Author's Affiliation | The University of Aizu (Univ. of Aizu) |
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| Speaker | Author-1 |
| Date Time | 2010-01-26 13:30:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2009-76, CPSY2009-58, RECONF2009-61 |
| Volume (vol) | vol.109 |
| Number (no) | no.393(VLD), no.394(CPSY), no.395(RECONF) |
| Page | pp.41-46 |
| #Pages | 6 |
| Date of Issue | 2010-01-19 (VLD, CPSY, RECONF) |
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