Paper Abstract and Keywords |
Presentation |
2010-01-28 14:00
[Invited Talk]
Realization of High Performance Computing using Massive-parallel Multi-core GPU
-- Computational Application of 512 32/64-bit processor cores integrated in a single-chip GPU -- Toru Baji (NV-Japan) ICD2009-108 Link to ES Tech. Rep. Archives: ICD2009-108 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
To meet the rapid evolution of rendering algorithm, PC/WS GPU has been implemented as a general-purpose multi-core GPU. Moreover, to meet the growing rendering performance requirement, the number of cores has been increased to the order of hundreds. To utilize this massive computational resource to computation applications, NVIDIA has developed a SW/HW architecture CUDA in 2006. By a hierarchical thread definition of the subject, HW can properly allocate threads to the cores making an efficient use of the massive-parallel processors. Peak single-precision floating-point performance of the latest GPU is exceeding 1-TFLOPS. This makes it easy to offer that level of performance in the daily life, that once could just achieved by Supercomputers. In this paper, the latest Fermi GPU architecture announced in late 2009 will also be described. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Multi Core / Massive Parallel / Many Cores / GPU / GPGPU / GPU Computing / CUDA / Fermi |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 405, ICD2009-108, pp. 39-44, Jan. 2010. |
Paper # |
ICD2009-108 |
Date of Issue |
2010-01-21 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2009-108 Link to ES Tech. Rep. Archives: ICD2009-108 |
Conference Information |
Committee |
ICD IPSJ-ARC IPSJ-EMB |
Conference Date |
2010-01-28 - 2010-01-29 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
T.B.D. |
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(See Japanese page) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2010-01-ICD-ARC-EMB |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Realization of High Performance Computing using Massive-parallel Multi-core GPU |
Sub Title (in English) |
Computational Application of 512 32/64-bit processor cores integrated in a single-chip GPU |
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Multi Core |
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Massive Parallel |
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Many Cores |
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GPU |
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GPGPU |
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GPU Computing |
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CUDA |
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Fermi |
1st Author's Name |
Toru Baji |
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NVIDIA Japan (NV-Japan) |
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Speaker |
Author-1 |
Date Time |
2010-01-28 14:00:00 |
Presentation Time |
45 minutes |
Registration for |
ICD |
Paper # |
ICD2009-108 |
Volume (vol) |
vol.109 |
Number (no) |
no.405 |
Page |
pp.39-44 |
#Pages |
6 |
Date of Issue |
2010-01-21 (ICD) |