IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2010-02-15 09:25
Test Pattern Re-Ordering for Thermal-Uniformity during Test
Makoto Nakao, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-66
Abstract (in Japanese) (See Japanese page) 
(in English) Power consumption during VLSI testing varies spatially and temporally, and it leads to temperature variation during test.This paper presents a thermal-uniformity-aware test pattern re-ordering method to reduce temperature dependent delay variation for accurate delay testing. In the proposed method, we first divide a given test pattern sequence into a set of subsequences, and then re-order them so that the maximum temperature difference during test is minimized. Experimental results show that the proposed method can achieve thermal uniformity while preserving the power optimization effects such as power minimization or power variation minimization of the given ordered test set.
Keyword (in Japanese) (See Japanese page) 
(in English) thermal-uniformity / test pattern re-ordering / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 416, DC2009-66, pp. 7-12, Feb. 2010.
Paper # DC2009-66 
Date of Issue 2010-02-08 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2009-66

Conference Information
Committee DC  
Conference Date 2010-02-15 - 2010-02-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2010-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Test Pattern Re-Ordering for Thermal-Uniformity during Test 
Sub Title (in English)  
Keyword(1) thermal-uniformity  
Keyword(2) test pattern re-ordering  
Keyword(3)  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Makoto Nakao  
1st Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology (Nara Inst. of Sci and Tech.)
2nd Author's Name Tomokazu Yoneda  
2nd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology (Nara Inst. of Sci and Tech.)
3rd Author's Name Michiko Inoue  
3rd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology (Nara Inst. of Sci and Tech.)
4th Author's Name Hideo Fujiwara  
4th Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology (Nara Inst. of Sci and Tech.)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2010-02-15 09:25:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2009-66 
Volume (vol) vol.109 
Number (no) no.416 
Page pp.7-12 
#Pages
Date of Issue 2010-02-08 (DC) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan