Paper Abstract and Keywords |
Presentation |
2010-02-15 09:25
Test Pattern Re-Ordering for Thermal-Uniformity during Test Makoto Nakao, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-66 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Power consumption during VLSI testing varies spatially and temporally, and it leads to temperature variation during test.This paper presents a thermal-uniformity-aware test pattern re-ordering method to reduce temperature dependent delay variation for accurate delay testing. In the proposed method, we first divide a given test pattern sequence into a set of subsequences, and then re-order them so that the maximum temperature difference during test is minimized. Experimental results show that the proposed method can achieve thermal uniformity while preserving the power optimization effects such as power minimization or power variation minimization of the given ordered test set. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
thermal-uniformity / test pattern re-ordering / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 416, DC2009-66, pp. 7-12, Feb. 2010. |
Paper # |
DC2009-66 |
Date of Issue |
2010-02-08 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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DC2009-66 |
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