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Paper Abstract and Keywords
Presentation 2010-02-23 10:35
Fabrication of nanowire-based sequential circuits using gate-controlled GaAs three-branch nanowire junctions
Hiromu Shibata, Daisuke Nakata, Yuta Shiratori (Hokkaido Univ), Seiya Kasai (Hokkaido Univ/JST) ED2009-207 SDM2009-204 Link to ES Tech. Rep. Archives: ED2009-207 SDM2009-204
Abstract (in Japanese) (See Japanese page) 
(in English) A novel sequential circuit integrating gate-controlled three-branch nanowire junctions (TBJs) is described. A TBJ shows a unique nonlinear voltage transfer characteristics even with a very simple structure connecting three nanowires. It can operate as a two-input AND gate by itself and NAND gate can be realized by integrating the TBJ and an inverter. The TBJ voltage transfer efficiency is improved by gate control of the input nanowires. This structure also has a DCFL inverter configuration. A set-reset flip flop (SR-FF) circuit is designed and fabricated by a GaAs-based etched nanowire network and its Schottky wrap gate control. A correct SR-FF operation of the fabricated circuit is successfully demonstrated.
Keyword (in Japanese) (See Japanese page) 
(in English) Three-branch Nanowire Junctions(TBJ) / GaAs / Sequential Circuit / Set-Reset Flip-Flop(SR-FF) / Nanowire Netwark / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 422, ED2009-207, pp. 65-70, Feb. 2010.
Paper # ED2009-207 
Date of Issue 2010-02-15 (ED, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ED2009-207 SDM2009-204 Link to ES Tech. Rep. Archives: ED2009-207 SDM2009-204

Conference Information
Committee ED SDM  
Conference Date 2010-02-22 - 2010-02-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawaken-Seinen-Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Functional Nano Device and Related Technology 
Paper Information
Registration To ED 
Conference Code 2010-02-ED-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fabrication of nanowire-based sequential circuits using gate-controlled GaAs three-branch nanowire junctions 
Sub Title (in English)  
Keyword(1) Three-branch Nanowire Junctions(TBJ)  
Keyword(2) GaAs  
Keyword(3) Sequential Circuit  
Keyword(4) Set-Reset Flip-Flop(SR-FF)  
Keyword(5) Nanowire Netwark  
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Keyword(7)  
Keyword(8)  
1st Author's Name Hiromu Shibata  
1st Author's Affiliation Hokkaido University (Hokkaido Univ)
2nd Author's Name Daisuke Nakata  
2nd Author's Affiliation Hokkaido University (Hokkaido Univ)
3rd Author's Name Yuta Shiratori  
3rd Author's Affiliation Hokkaido University (Hokkaido Univ)
4th Author's Name Seiya Kasai  
4th Author's Affiliation Hokkaido University/PRESTO, JST (Hokkaido Univ/JST)
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Speaker Author-1 
Date Time 2010-02-23 10:35:00 
Presentation Time 25 minutes 
Registration for ED 
Paper # ED2009-207, SDM2009-204 
Volume (vol) vol.109 
Number (no) no.422(ED), no.423(SDM) 
Page pp.65-70 
#Pages
Date of Issue 2010-02-15 (ED, SDM) 


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