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| Presentation | 2010-03-11 10:00 Study of Via Programmable Logic Device VPEX for wiring architecture and Logic Array Block Shouta Yamada, Yuuichi Kokushou, Tomohiro Nishimoto, Naoyuki Yoshida, Ryohei Hori, Naoki Matsumoto, Tatsuya Kitamori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijou Univ.), Takeshi Fujino (Ritsumeikan Univ.)  VLD2009-107 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We have developed the via-programmable logic device VPEX which was optimized for EB direct writing, and also developed the dedicated CAD system for the VPEX. The VPEX logic element composed of complex-gate type exclusive OR gate and inverters can be configured to one of 2-input logic functions or 3-input logic functions such as AOI and multiplexer with via-1 layer. The routing between LEs can be programmed by the via-3 layer which change connections between fixed metal-3 and metal-4 layers. Thus, the routing architecture and routing resources of each LE affect the wiring success ratio greatly. In this paper, we examine several routing architectures to improve the routability. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Via-programmable logic / Dedicated CAD system / Wire congestion / Routing architecture / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 462, VLD2009-107, pp. 49-54, March 2010. | |
| Paper # | VLD2009-107 | |
| Date of Issue | 2010-03-03 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-107 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2010-03-10 - 2010-03-12 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2010-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study of Via Programmable Logic Device VPEX for wiring architecture and Logic Array Block |
| Sub Title (in English) | |
| Keyword(1) | Via-programmable logic |
| Keyword(2) | Dedicated CAD system |
| Keyword(3) | Wire congestion |
| Keyword(4) | Routing architecture |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Shouta Yamada |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Yuuichi Kokushou |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 3rd Author's Name | Tomohiro Nishimoto |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name | Naoyuki Yoshida |
| 4th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 5th Author's Name | Ryohei Hori |
| 5th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 6th Author's Name | Naoki Matsumoto |
| 6th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 7th Author's Name | Tatsuya Kitamori |
| 7th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 8th Author's Name | Masaya Yoshikawa |
| 8th Author's Affiliation | Meijou University (Meijou Univ.) |
| 9th Author's Name | Takeshi Fujino |
| 9th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2010-03-11 10:00:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2009-107 |
| Volume (vol) | vol.109 |
| Number (no) | no.462 |
| Page | pp.49-54 |
| #Pages | 6 |
| Date of Issue | 2010-03-03 (VLD) |
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