Paper Abstract and Keywords |
Presentation |
2010-08-27 10:15
[Invited Talk]
Development of sub-10um Thinning Technology using Actual Device Wafers Nobuhide Maeda, Kim Youngsuk (Univ. of Tokyo), Yukinobu Hikosaka, Takashi Eshita (FSL), Hideki Kitada, Koji Fujimoto (Univ. of Tokyo), Yoriko Mizushima (Fujitsu Labs.), Kousuke Suzuki (DNP), Tomoji Nakamura (Fujitsu Labs.), Akihito Kawai, Kazuhisa Arai (DISCO), Takayuki Ohba (Univ. of Tokyo) SDM2010-141 ICD2010-56 Link to ES Tech. Rep. Archives: SDM2010-141 ICD2010-56 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
200-mm and 300-mm device wafers were successfully thinned down to less than 10-μm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-μm, switching charge showed no change by the thinning process. CMOS logic device wafers thinned to 7-μm indicated neither change in Ion current nor junction leakage current. Thinning such wafers to <10-μm will allow for lower aspect ratio less than 4 of Through-Silicon-Via (TSV) in a via-last process. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
3D Integration / Wafer thinning / WOW / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 182, SDM2010-141, pp. 95-97, Aug. 2010. |
Paper # |
SDM2010-141 |
Date of Issue |
2010-08-19 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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SDM2010-141 ICD2010-56 Link to ES Tech. Rep. Archives: SDM2010-141 ICD2010-56 |
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