Paper Abstract and Keywords |
Presentation |
2010-12-16 13:50
High Error Rate Compensation Architecture and ECC for SSDs with NV-RAM and NAND Flash Kazuhide Higuchi, Mayumi Fukuda, Shuhei Tanakamaru, Ken Takeuchi (Univ. Tokyo) ICD2010-99 Link to ES Tech. Rep. Archives: ICD2010-99 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we propose the adaptive codeword ECC (Error Correcting Code) for NV-RAM (Non Volatile RAM) and NAND flash memory integrated SSD (Solid-State Drive) to improve the memory cell reliability. In the proposed SSD, NV-RAM such as RRAM, PRAM and MRAM is used as write buffers. The NV-RAM write buffer compensates the performance gap between the NAND flash memory and the SSD interface. Errors of NV-RAM and NAND are most efficiently corrected and reliability improves through error correcting circuit without area overhead. By using NV-RAM as write buffers, the 10Gbps write is achieved with a significant power reduction. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Flash memory / Nonvolatile RAM / SSD / ECC / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 344, ICD2010-99, pp. 25-30, Dec. 2010. |
Paper # |
ICD2010-99 |
Date of Issue |
2010-12-09 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2010-99 Link to ES Tech. Rep. Archives: ICD2010-99 |
Conference Information |
Committee |
ICD |
Conference Date |
2010-12-16 - 2010-12-17 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
RCAST, Univ. of Tokyo |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Workshop for Graduate Student and Young Researchers |
Paper Information |
Registration To |
ICD |
Conference Code |
2010-12-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
High Error Rate Compensation Architecture and ECC for SSDs with NV-RAM and NAND Flash |
Sub Title (in English) |
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Keyword(1) |
Flash memory |
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Nonvolatile RAM |
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SSD |
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ECC |
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1st Author's Name |
Kazuhide Higuchi |
1st Author's Affiliation |
The University of Tokyo (Univ. Tokyo) |
2nd Author's Name |
Mayumi Fukuda |
2nd Author's Affiliation |
The University of Tokyo (Univ. Tokyo) |
3rd Author's Name |
Shuhei Tanakamaru |
3rd Author's Affiliation |
The University of Tokyo (Univ. Tokyo) |
4th Author's Name |
Ken Takeuchi |
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The University of Tokyo (Univ. Tokyo) |
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Speaker |
Author-1 |
Date Time |
2010-12-16 13:50:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
ICD2010-99 |
Volume (vol) |
vol.110 |
Number (no) |
no.344 |
Page |
pp.25-30 |
#Pages |
6 |
Date of Issue |
2010-12-09 (ICD) |
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