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Paper Abstract and Keywords
Presentation 2011-01-18 14:50
Silent Large Datapath : A Ultra Low Power Accelarater
Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-109 CPSY2010-64 RECONF2010-78
Abstract (in Japanese) (See Japanese page) 
(in English) Silent Large Datapath (SLD) is a low power reconfigurable accelerator for high performance embedded
systems. By using a large PE (Processing Element) array consisting of pure combinatorial circuits, the overhead
for clock distribution and storing/reading intermediate results to/from registers can be omitted. A small microcontroller
manages distribution and collection of data between PE array and data memory module for flexible data
allocation to the fixed datapath on the PE array. Dynamic voltage scaling is applied for the whole PE array and
the energy of the PE array can be saved by using the slack time of the datapath. Compared with corresponding
pipelined accelerator, SLD can achieve 29% improvement of energy efficiency.
Keyword (in Japanese) (See Japanese page) 
(in English) Reconfigurable Processor Array / Low Power / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 362, RECONF2010-78, pp. 169-174, Jan. 2011.
Paper # RECONF2010-78 
Date of Issue 2011-01-10 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2010-109 CPSY2010-64 RECONF2010-78

Conference Information
Committee RECONF VLD CPSY IPSJ-SLDM  
Conference Date 2011-01-17 - 2011-01-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ (Hiyoshi Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2011-01-RECONF-VLD-CPSY-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Silent Large Datapath : A Ultra Low Power Accelarater 
Sub Title (in English)  
Keyword(1) Reconfigurable Processor Array  
Keyword(2) Low Power  
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1st Author's Name Yoshihiro Yasuda  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Nobuaki Ozaki  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Masayuki Kimura  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Yoshiki Saito  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Daisuke Ikebuchi  
5th Author's Affiliation Keio University (Keio Univ.)
6th Author's Name Hideharu Amano  
6th Author's Affiliation Keio University (Keio Univ.)
7th Author's Name Hiroshi Nakamura  
7th Author's Affiliation The University of Tokyo (Univ. of Tokyo)
8th Author's Name Kimiyoshi Usami  
8th Author's Affiliation Shibaura Institute of technology (Shibaura Inst. Tech.)
9th Author's Name Mitaro Namiki  
9th Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Tech.)
10th Author's Name Masaaki Kondo  
10th Author's Affiliation The University of Electro-Communications (Univ. of Electro-Communications)
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Speaker Author-1 
Date Time 2011-01-18 14:50:00 
Presentation Time 20 minutes 
Registration for RECONF 
Paper # VLD2010-109, CPSY2010-64, RECONF2010-78 
Volume (vol) vol.110 
Number (no) no.360(VLD), no.361(CPSY), no.362(RECONF) 
Page pp.169-174 
#Pages
Date of Issue 2011-01-10 (VLD, CPSY, RECONF) 


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