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| Presentation | 2011-01-18 14:30 Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.)  VLD2010-108 CPSY2010-63 RECONF2010-77 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recently, System on a Chip (SoC) has problems increasing of the scale of circuit and design cost, because SoC contains many types of application specific hardware modules. We expect that these problems can be solved by reconfigurable devices. In this paper, we propose dynamic reconfigurable processor architecture with multi-accelerators using Dynamic Partial Reconfiguration (DPR) technology which is implemented in some FPGAs provided by XILINX. The proposed processor system with multi-accelerator partially reconfigured on multi-regions is implemented and evaluated about circuit size and reconfiguration time. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Hardware Accelerator / Reconfigurable Device / Dynamic Partial Reconfiguration / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 362, RECONF2010-77, pp. 163-168, Jan. 2011. | |
| Paper # | RECONF2010-77 | |
| Date of Issue | 2011-01-10 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2010-108 CPSY2010-63 RECONF2010-77 |
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| Conference Information | |
| Committee | RECONF VLD CPSY IPSJ-SLDM |
| Conference Date | 2011-01-17 - 2011-01-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Keio Univ (Hiyoshi Campus) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2011-01-RECONF-VLD-CPSY-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator |
| Sub Title (in English) | |
| Keyword(1) | Hardware Accelerator |
| Keyword(2) | Reconfigurable Device |
| Keyword(3) | Dynamic Partial Reconfiguration |
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| 1st Author's Name | Shuhei Igari |
| 1st Author's Affiliation | University of Aizu (Aizu Univ.) |
| 2nd Author's Name | Junji Kitamichi |
| 2nd Author's Affiliation | University of Aizu (Aizu Univ.) |
| 3rd Author's Name | Yuichi Okuyama |
| 3rd Author's Affiliation | University of Aizu (Aizu Univ.) |
| 4th Author's Name | Kenichi Kuroda |
| 4th Author's Affiliation | University of Aizu (Aizu Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-01-18 14:30:00 |
| Presentation Time | 20 minutes |
| Registration for | RECONF |
| Paper # | VLD2010-108, CPSY2010-63, RECONF2010-77 |
| Volume (vol) | vol.110 |
| Number (no) | no.360(VLD), no.361(CPSY), no.362(RECONF) |
| Page | pp.163-168 |
| #Pages | 6 |
| Date of Issue | 2011-01-10 (VLD, CPSY, RECONF) |
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