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Paper Abstract and Keywords
Presentation 2011-03-03 10:50
A Modular Low Cost Hardware TCP/IP Stack Implementation Adding Direct Network Capabilities to Same On-Chip Embedded Applications Using Xilinx Spartan3 FPGA
Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (Tokyo Univ. of Agric and Tech.) CAS2010-128 SIP2010-144 CS2010-98
Abstract (in Japanese) (See Japanese page) 
(in English) As multi-processor based computers and electronic devices become the norm,
a further emphasis is made on achieving tasks by means of low power parallel processing.
Furthermore, with the growth of Internet-based rich multimedia applications,
these tasks would often require high speed network capabilities readily available.
An FPGA, unlike ASIC implementations which are difficult to adopt for their lack of standards,
would allow us to develop flexible and power-efficient high-speed processing systems capable
of addressing the tasks at hand.

In previous works we have introduced a remotely reconfigurable hardware/software complex system which is capable of exchanging virtual hardware circuits over Ethernet, as well as a proof of concept client-server architecture based web application that compresses and streams video in hardware, achieving a full-color VGA size (24bits RGB, 640x480 pixels) 20 fps video stream with throughput of 10.8Mbps.

In this paper we propose a hardware TCP/IP stack implementation as an extension to this model, to enable Internet connectivity and to accelerate networking multimedia transmission.
This TCP/IP stack is both modular, allowing direct connection of embedded applications without CPU or PCI bus resource usage through a common on-chip bus architecture, and extensible as it consists of independent blocks that can easily be changed in order to support future changes in protocols.
This framework simplifies the development of networking applications since Internet Protocol (IP) packets, UDP datagrams and TCP segments are all directly processed in hardware.

A software application needs only to interact with a memory buffer to use the network resources of the system.
The applications of this modular TCP/IP stack vary in a wide range of devices such as multimedia content based devices, robotics and network security appliances. These
applications will be able not only to gather and distribute information, but
also to be reconfigured through the web.
The proposed system is implemented in Xilinx's low-end Spartan3 FPGA, which operates at 66MHz with achieved throughput of 100Mbps.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / TCP/IP / UDP / Network on chip / hw/sw complex system / Ethernet / Reconfigurable hardware /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 439, CAS2010-128, pp. 155-160, March 2011.
Paper # CAS2010-128 
Date of Issue 2011-02-24 (CAS, SIP, CS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2010-128 SIP2010-144 CS2010-98

Conference Information
Committee CS SIP CAS  
Conference Date 2011-03-03 - 2011-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Ohhamanobumoto memorial hall (Ishigaki)( 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Network Processor, Signal Processing for Communications, Wireless LAN/PAN, etc. 
Paper Information
Registration To CAS 
Conference Code 2011-03-CS-SIP-CAS 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Modular Low Cost Hardware TCP/IP Stack Implementation Adding Direct Network Capabilities to Same On-Chip Embedded Applications Using Xilinx Spartan3 FPGA 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) TCP/IP  
Keyword(3) UDP  
Keyword(4) Network on chip  
Keyword(5) hw/sw complex system  
Keyword(6) Ethernet  
Keyword(7) Reconfigurable hardware  
Keyword(8)  
1st Author's Name Nadav Bergstein  
1st Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agric and Tech.)
2nd Author's Name Hakaru Tamukoh  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agric and Tech.)
3rd Author's Name Masatoshi Sekine  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agric and Tech.)
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Speaker Author-1 
Date Time 2011-03-03 10:50:00 
Presentation Time 20 minutes 
Registration for CAS 
Paper # CAS2010-128, SIP2010-144, CS2010-98 
Volume (vol) vol.110 
Number (no) no.439(CAS), no.440(SIP), no.441(CS) 
Page pp.155-160 
#Pages
Date of Issue 2011-02-24 (CAS, SIP, CS) 


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