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| Presentation | 2011-03-04 11:40 Investigation on Japan ISDB-T 1SEG Software Defined Radio Signal Processing on PC Platform Yuichiro Sunagawa, Tomohisa Wada (Univ. of the Ryukyus.)  CAS2010-161 SIP2010-177 CS2010-131 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Software Defined Radio (SDR) has received a strong attention in the development of digital communication system. Since SDR approach replaces Hardware digital circuits with microprocessors with Software, not only system flexibility but also system cost and development time can be reduced simultaneously. This paper proposes SDR architecture for Japanese digital TV (ISDB-T) 1-segment receiver and shows the performance measurement results on PC platform. The system includes demodulation part such as synchronization, FFT, equalizer. Then the digitized IF signal is demodulated and the QPSK consternation is output. Assuming the low cost analog tuner device as a front-end, carrier frequency adjustment and clock frequency recovery mechanism are also implemented in Software. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Software Defined Radio (SDR) / 1seg / OFDM / Equalizer / Resampler / Symbol Synchronization / FFT / | |
| Reference Info. | IEICE Tech. Rep., vol. 110, no. 440, SIP2010-177, pp. 347-352, March 2011. | |
| Paper # | SIP2010-177 | |
| Date of Issue | 2011-02-24 (CAS, SIP, CS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2010-161 SIP2010-177 CS2010-131 |
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| Conference Information | |
| Committee | CS SIP CAS |
| Conference Date | 2011-03-03 - 2011-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ohhamanobumoto memorial hall (Ishigaki)( |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Network Processor, Signal Processing for Communications, Wireless LAN/PAN, etc. |
| Paper Information | |
| Registration To | SIP |
| Conference Code | 2011-03-CS-SIP-CAS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Investigation on Japan ISDB-T 1SEG Software Defined Radio Signal Processing on PC Platform |
| Sub Title (in English) | |
| Keyword(1) | Software Defined Radio (SDR) |
| Keyword(2) | 1seg |
| Keyword(3) | OFDM |
| Keyword(4) | Equalizer |
| Keyword(5) | Resampler |
| Keyword(6) | Symbol Synchronization |
| Keyword(7) | FFT |
| Keyword(8) | |
| 1st Author's Name | Yuichiro Sunagawa |
| 1st Author's Affiliation | University of the Ryukyus (Univ. of the Ryukyus.) |
| 2nd Author's Name | Tomohisa Wada |
| 2nd Author's Affiliation | University of the Ryukyus (Univ. of the Ryukyus.) |
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| Speaker | Author-1 |
| Date Time | 2011-03-04 11:40:00 |
| Presentation Time | 20 minutes |
| Registration for | SIP |
| Paper # | CAS2010-161, SIP2010-177, CS2010-131 |
| Volume (vol) | vol.110 |
| Number (no) | no.439(CAS), no.440(SIP), no.441(CS) |
| Page | pp.347-352 |
| #Pages | 6 |
| Date of Issue | 2011-02-24 (CAS, SIP, CS) |
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