Paper Abstract and Keywords |
Presentation |
2011-04-12 16:35
Highly Flexible Task Tracer IP for the Real-Time OS on FPGA/SoC Environments Yuji Takeda, Mamoru Ohara, Tadashi Okabe, Ken Sato (Tokyo Metro. Indust. Tech. Res. Inst.) CPSY2011-7 DC2011-7 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, the use of RTOS is advanced in a multi-core processor on FPGA/SoC, and to watch the task transitions is important when confirm dead lock conditions and operations of realtime processing.
However, the conventional methods by using software hook processes or processor specific hardware, i.e. the ICE, are not suitable for long realtime monitoring without processor loading.
Then, we have developed a task tracer IP to extract only task transitions by snooping a general-purpose bus of FPGA/SoC.
This IP consists of several taps and a master, and the selectivity of communication I/F that transmits the trace data and the core scalability are improved.
Moreover, it can compress the trace data by difference operations and variable length coding.
It was confirmed to reduce the traffic by 46.6\% as a result of really tracing the TCB access by the TOPPERS kernel. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA/SoC / multi-core processor / RTOS (Real-Time OS) / task trace / data compression / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 1, CPSY2011-7, pp. 35-40, April 2011. |
Paper # |
CPSY2011-7 |
Date of Issue |
2011-04-05 (CPSY, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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CPSY2011-7 DC2011-7 |
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