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Paper Abstract and Keywords
Presentation 2011-05-13 17:15
Candidate Fault Portions Detection using CMOS Transistor Operation Point Analysis
Kazuaki Kishi, Masaru Sanada (KUT) R2011-14
Abstract (in Japanese) (See Japanese page) 
(in English) We have developed fault diagnosis software with easy operation, high diagnosis accuracy and fast processing speed. The technology is the way to embed the candidate fault pattern in fault area circuit detected by public technique, and to calculate output voltage value in it. The former fault patterns are adjoin-lines crossed-lines and via-holes. The latter output voltage calculate is based on analysis of Transistor operation point. First, the method is to take out penetration current net from in the candidate fault area, to calculate impedance value of Tr on the current net, to form impedance (Z)net, next to calculate voltage value each the net node, and to decide the portion accord with real fault logic as defect point. Z value is determined using Tr geometry (L/W) and Tr operation point synchronized with gate voltage. The report is introduced the structure of software and algorithm.
Keyword (in Japanese) (See Japanese page) 
(in English) LSI / CMOS / Fault Diagnosis / Operation Point Analysis / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 33, R2011-14, pp. 35-40, May 2011.
Paper # R2011-14 
Date of Issue 2011-05-06 (R) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee R  
Conference Date 2011-05-13 - 2011-05-13 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi City Culture-Plaza Cul-Port 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To R 
Conference Code 2011-05-R 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Candidate Fault Portions Detection using CMOS Transistor Operation Point Analysis 
Sub Title (in English)  
Keyword(1) LSI  
Keyword(2) CMOS  
Keyword(3) Fault Diagnosis  
Keyword(4) Operation Point Analysis  
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1st Author's Name Kazuaki Kishi  
1st Author's Affiliation Kochi University of Technology (KUT)
2nd Author's Name Masaru Sanada  
2nd Author's Affiliation Kochi University of Technology (KUT)
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Speaker Author-1 
Date Time 2011-05-13 17:15:00 
Presentation Time 25 minutes 
Registration for R 
Paper # R2011-14 
Volume (vol) vol.111 
Number (no) no.33 
Page pp.35-40 
#Pages
Date of Issue 2011-05-06 (R) 


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