Paper Abstract and Keywords |
Presentation |
2011-07-01 16:10
Hardware Implementation of Two-Dimensional Non-separable GenLOT Based on Block Processing and Lifting Scheme Yuya Ota (Niigata Univ.), Saemi Choi (Inha Univ.), Shogo Muramatsu, Hisakazu Kikuchi (Niigata Univ.) CAS2011-30 VLD2011-37 SIP2011-59 MSS2011-30 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this report, a hardware architecture of two-dimensional non-separable GenLOT is proposed based onthe block processing and lifting scheme. The discrete cosine transform (DCT) adopted in JPEG and MPEG-2, or the
discrete wavelet transform (DWT) used in JPEG2000 are not suitable for the expression of diagonal textures and edges because these transforms are separable. The non-separable GenLOT proposed by the authors is suitable for the expression of diagonal textures and edges because it can take directionality and has block-wise implementation which maintains the orthogonality. However, there is a problem in the process in teams of the computational cost. It is expected that a specic hardware yields effective solution to this problem. Therefore, in this study, it is suggested to realize the two-dimensional non-separable GenLOT on hardware architecture by the block-wise handling and lifting scheme. The circuit module to be implemented on hardware is modeled by VHDL and the speed and area are evaluated from the synthesis reports. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Non-separable GenLOT / DCT / DWT / FPGA / Lifting Scheme / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 104, SIP2011-59, pp. 169-174, June 2011. |
Paper # |
SIP2011-59 |
Date of Issue |
2011-06-23 (CAS, VLD, SIP, MSS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2011-30 VLD2011-37 SIP2011-59 MSS2011-30 |
Conference Information |
Committee |
MSS CAS VLD SIP |
Conference Date |
2011-06-30 - 2011-07-01 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa-Ken-Seinen-Kaikan |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
SIP |
Conference Code |
2011-06-MSS-CAS-VLD-SIP |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Hardware Implementation of Two-Dimensional Non-separable GenLOT Based on Block Processing and Lifting Scheme |
Sub Title (in English) |
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Keyword(1) |
Non-separable GenLOT |
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DCT |
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DWT |
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FPGA |
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Lifting Scheme |
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1st Author's Name |
Yuya Ota |
1st Author's Affiliation |
Niigata University (Niigata Univ.) |
2nd Author's Name |
Saemi Choi |
2nd Author's Affiliation |
Inha University (Inha Univ.) |
3rd Author's Name |
Shogo Muramatsu |
3rd Author's Affiliation |
Niigata University (Niigata Univ.) |
4th Author's Name |
Hisakazu Kikuchi |
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Niigata University (Niigata Univ.) |
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Speaker |
Author-1 |
Date Time |
2011-07-01 16:10:00 |
Presentation Time |
20 minutes |
Registration for |
SIP |
Paper # |
CAS2011-30, VLD2011-37, SIP2011-59, MSS2011-30 |
Volume (vol) |
vol.111 |
Number (no) |
no.102(CAS), no.103(VLD), no.104(SIP), no.105(MSS) |
Page |
pp.169-174 |
#Pages |
6 |
Date of Issue |
2011-06-23 (CAS, VLD, SIP, MSS) |
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