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| Presentation | 2011-10-21 09:50 Study of Mixed Power Gating on VLIW Processors Yoshifumi Ishii, Weihan Wang, Hideharu Amano (Keio Univ.)  CPSY2011-26 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Power Gating (PG) is an effective way to reduce leakage power that becomes a big issue in LSI designs. There are two ways to implement PG: fine-grained PG and coarse-grained PG. In fine-grained PG, sleep control can be done quickly but area overhead is large, while coarse-grained PG can be implemented with small area overhead. By combining them, we proposed a mixed grain power gating and designed VLIW processors which it is applied to, Geyser-VLIW. Through the evaluation of leakage power at 25C, on MiBench QSORT, the leakage power can be reduced by 9.13% in the case of sleeping only fing-grained PG circuits, and it can be reduced by 25.1% in the case of sleeping both fing-grained PG circuits and coarse-grained PG circuits. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Low Power / Power Gating / Processor / VLIW / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 255, CPSY2011-26, pp. 7-12, Oct. 2011. | |
| Paper # | CPSY2011-26 | |
| Date of Issue | 2011-10-14 (CPSY) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2011-26 |
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| Conference Information | |
| Committee | CPSY |
| Conference Date | 2011-10-21 - 2011-10-21 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2011-10-CPSY |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study of Mixed Power Gating on VLIW Processors |
| Sub Title (in English) | |
| Keyword(1) | Low Power |
| Keyword(2) | Power Gating |
| Keyword(3) | Processor |
| Keyword(4) | VLIW |
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| 1st Author's Name | Yoshifumi Ishii |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Weihan Wang |
| 2nd Author's Affiliation | Keio University (Keio Univ.) |
| 3rd Author's Name | Hideharu Amano |
| 3rd Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-10-21 09:50:00 |
| Presentation Time | 20 minutes |
| Registration for | CPSY |
| Paper # | CPSY2011-26 |
| Volume (vol) | vol.111 |
| Number (no) | no.255 |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2011-10-14 (CPSY) |
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