Paper Abstract and Keywords |
Presentation |
2011-10-25 13:55
Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-74 ICD2011-77 IE2011-73 Link to ES Tech. Rep. Archives: ICD2011-77 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Accelerator cores in low-power heterogeneous multicore processors have multiple memory modules to increase the data access speed and to enable parallel data access. Recent low-power processors contain address generation units (AGUs) for fast address generation. To reduce the core-area, small functional units such as adders and counters are used in AGUs. Such small functional units make it difficult to implement complex addressing patterns without duplicating the data among multiple memory modules. The data-duplication wastes the memory capacity and increases the data transfer time significantly. This paper proposes a method to remove the memory duplication and to increase the degree of parallelism. To verify the effectiveness of this method, we use window-based media processing which is widely used in many applications. According to the evaluation, the proposed method reduces the total processing time by 14\% to more than 85\% compared to the previous works. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Heterogeneous multicore / memory allocation / dynamic reconfiguration / multi-context FPGA / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 258, ICD2011-77, pp. 77-82, Oct. 2011. |
Paper # |
ICD2011-77 |
Date of Issue |
2011-10-17 (SIP, ICD, IE) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SIP2011-74 ICD2011-77 IE2011-73 Link to ES Tech. Rep. Archives: ICD2011-77 |
Conference Information |
Committee |
ICD IE SIP IPSJ-SLDM |
Conference Date |
2011-10-24 - 2011-10-25 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Ichinobo(Sendai) |
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(See Japanese page) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2011-10-ICD-IE-SIP-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors |
Sub Title (in English) |
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Keyword(1) |
Heterogeneous multicore |
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memory allocation |
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dynamic reconfiguration |
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multi-context FPGA |
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1st Author's Name |
Yosuke Ohbayashi |
1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
2nd Author's Name |
Hasitha Muthumala Waidyasooriya |
2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
3rd Author's Name |
Masanori Hariyama |
3rd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
4th Author's Name |
Michitaka Kameyama |
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Tohoku University (Tohoku Univ.) |
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Speaker |
Author-1 |
Date Time |
2011-10-25 13:55:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
SIP2011-74, ICD2011-77, IE2011-73 |
Volume (vol) |
vol.111 |
Number (no) |
no.257(SIP), no.258(ICD), no.259(IE) |
Page |
pp.77-82 |
#Pages |
6 |
Date of Issue |
2011-10-17 (SIP, ICD, IE) |
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