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| Presentation | 2011-11-11 15:45 Higher-order Effects of Source and Drain Parasitic Resistances for Nanoscale MOSFETs Jong Chul Yoon, Akira Hiroki (Kyoto Institute of Tech.)  SDM2011-129 Link to ES Tech. Rep. Archives: SDM2011-129 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Higher-order effects of source and drain parasitic resistances have been investigated for nanoscale MOSFETs. We have derived a saturation current model including the higher-order effects of parasitic resistances. The model was applied to 18nm MOSFET. The errors using the 1st order, 2nd order and 3rd order approximation are 10.1%, 3.2% and 1.0%, respectively. Each higher-order term is divided into 3 parts. It is found that the ratio of source and drain parasitic resistances to channel resistance is significant. It is essential to reduce this ratio for nanoscale MOSFET design. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | source and drain resistances / analytical MOSFET model / nanoscale MOSFETs / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 281, SDM2011-129, pp. 81-85, Nov. 2011. | |
| Paper # | SDM2011-129 | |
| Date of Issue | 2011-11-03 (SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2011-129 Link to ES Tech. Rep. Archives: SDM2011-129 |
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| Conference Information | |
| Committee | SDM |
| Conference Date | 2011-11-10 - 2011-11-11 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Process, Device, Circuit Simulations, etc |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2011-11-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Higher-order Effects of Source and Drain Parasitic Resistances for Nanoscale MOSFETs |
| Sub Title (in English) | |
| Keyword(1) | source and drain resistances |
| Keyword(2) | analytical MOSFET model |
| Keyword(3) | nanoscale MOSFETs |
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| 1st Author's Name | Jong Chul Yoon |
| 1st Author's Affiliation | Kyoto Institute of Technology (Kyoto Institute of Tech.) |
| 2nd Author's Name | Akira Hiroki |
| 2nd Author's Affiliation | Kyoto Institute of Technology (Kyoto Institute of Tech.) |
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| Speaker | Author-1 |
| Date Time | 2011-11-11 15:45:00 |
| Presentation Time | 25 minutes |
| Registration for | SDM |
| Paper # | SDM2011-129 |
| Volume (vol) | vol.111 |
| Number (no) | no.281 |
| Page | pp.81-85 |
| #Pages | 5 |
| Date of Issue | 2011-11-03 (SDM) |
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