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Paper Abstract and Keywords
Presentation 2011-11-28 13:25
Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops
Shogo Okada, Masaki Masuda (KIT), Jun Yao, Hajime Shimada (NAIST), Kazutoshi Kobayashi (KIT) VLD2011-59 DC2011-35
Abstract (in Japanese) (See Japanese page) 
(in English) Soft-error rates are becoming larger due to process scaling. Various ways of prediction for soft-error
are being tried. In this paper, we measure power dissipation of two soft-error tolerant multiple-modular processors
implemented with redundant and non-redundant flip-flops in 180nm, respectively. Redundant flip-flops have about
3x power and area than non-redundant flip-flops. The processor with redundant flip-flops has only 1.28x power and
1.71x area than the processor with non-redundant flip-flops.
Keyword (in Japanese) (See Japanese page) 
(in English) Power / Area / Multiple Modular Processor / Redundant FF / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 324, VLD2011-59, pp. 43-48, Nov. 2011.
Paper # VLD2011-59 
Date of Issue 2011-11-21 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2011-59 DC2011-35

Conference Information
Conference Date 2011-11-28 - 2011-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) NewWelCity Miyazaki 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops 
Sub Title (in English)  
Keyword(1) Power  
Keyword(2) Area  
Keyword(3) Multiple Modular Processor  
Keyword(4) Redundant FF  
1st Author's Name Shogo Okada  
1st Author's Affiliation Kyoto Institute of Technology (KIT)
2nd Author's Name Masaki Masuda  
2nd Author's Affiliation Kyoto Institute of Technology (KIT)
3rd Author's Name Jun Yao  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
4th Author's Name Hajime Shimada  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
5th Author's Name Kazutoshi Kobayashi  
5th Author's Affiliation Kyoto Institute of Technology (KIT)
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Speaker Author-1 
Date Time 2011-11-28 13:25:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2011-59, DC2011-35 
Volume (vol) vol.111 
Number (no) no.324(VLD), no.325(DC) 
Page pp.43-48 
Date of Issue 2011-11-21 (VLD, DC) 

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