Paper Abstract and Keywords |
Presentation |
2012-01-25 15:45
A bandwidth control scheme based on a traffic analysis for an on-chip router Daiki Yamazaki, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) VLD2011-101 CPSY2011-64 RECONF2011-60 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recent advances in embedded applications have demanded multi-core processors for embedded systems, and Network-on-Chip (NoC) has been used to interconnect multiple cores on a chip. Homogeneous NoCs that consist of identical routers are not efficient if applications have communication locality. In embedded systems, since applications are optimized and their communication pattern can be analyzed at design time, we can further improve the area and performance of NoC by optimizing data width for each link in response to the communication pattern. Toward such optimized heterogeneous NoCs, we present variable-bitwidth router architecture and a traffic analysis algorithm that selects data width for each link. In the evaluations, optimized heterogeneous NoCs are compared with uniform homogeneous NoCs in terms of area and throughput. The results show that the variable-bitwidth routers with the traffic analysis algorithm can significantly improve the area and performance. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
On-chip networks / Network-on-Chip (NoC) / bandwidth control / traffic analysis / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 398, CPSY2011-64, pp. 61-66, Jan. 2012. |
Paper # |
CPSY2011-64 |
Date of Issue |
2012-01-18 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2011-101 CPSY2011-64 RECONF2011-60 |
Conference Information |
Committee |
VLD CPSY RECONF IPSJ-SLDM |
Conference Date |
2012-01-25 - 2012-01-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
CPSY |
Conference Code |
2012-01-VLD-CPSY-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A bandwidth control scheme based on a traffic analysis for an on-chip router |
Sub Title (in English) |
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Keyword(1) |
On-chip networks |
Keyword(2) |
Network-on-Chip (NoC) |
Keyword(3) |
bandwidth control |
Keyword(4) |
traffic analysis |
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1st Author's Name |
Daiki Yamazaki |
1st Author's Affiliation |
Keio University (Keio Univ.) |
2nd Author's Name |
Hiroki Matsutani |
2nd Author's Affiliation |
Keio University (Keio Univ.) |
3rd Author's Name |
Nobuyuki Yamasaki |
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Keio University (Keio Univ.) |
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Speaker |
Author-1 |
Date Time |
2012-01-25 15:45:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
VLD2011-101, CPSY2011-64, RECONF2011-60 |
Volume (vol) |
vol.111 |
Number (no) |
no.397(VLD), no.398(CPSY), no.399(RECONF) |
Page |
pp.61-66 |
#Pages |
6 |
Date of Issue |
2012-01-18 (VLD, CPSY, RECONF) |
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