Paper Abstract and Keywords |
Presentation |
2012-03-06 11:00
LSI Implementation of Heterogeneous Multi-Chip Processor for energy-saving Embedded Systems : COOL Chip Hiroyuki Uchida, Michiya Hagimoto, Tomoyuki Morimoto, Nobuyuki Hikichi, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Naoya Watanabe, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) VLD2011-122 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The authors have suggested the low-power embedded heterogeneous multi-chip processor system: COOL Chip. We designed two prototype chips based on COOL Chip technology. Each chip has divided into more than 20 power domains so as to be able to observe dynamic power profile during application execution. This article describes the power evaluation method of COOL Chip prototype chips and the effectiveness for system-level power modeling. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Heterogeneous Multi-core Processor / System-Level Power Modeling / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 450, VLD2011-122, pp. 13-17, March 2012. |
Paper # |
VLD2011-122 |
Date of Issue |
2012-02-28 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2011-122 |