Paper Abstract and Keywords |
Presentation |
2012-03-06 15:55
Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools Takehiro Mikami, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2011-130 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A circuit has many false paths on which signal transitions never affect its circuit behavior.This report proposes a logic optimization method with logic synthesis tools in a situation where register transfer level (RTL) false paths are given.By using RTL false path infomation in logic synthesis, there is no need to consider the delay on false paths, and it can lead to an optimized circuit in terms of delay and area. In addition, this observation motivates us to select only a subset of given false paths so that an optimized circuit can be obtained in a reasonable amount of time. The characteristics of such false paths can be analyzed from various synthesis results in a preliminary experiment. On the basis of the analysis, this report presents a false path selection algorithm for logic synthesis. Experimental results show that the proposed false path selection algorithm is effective in reducing area, delay and synthesis time compared with some possible false path selection methods. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
register transfer level false path / logic synthesis / logic optimization / false path selection / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 450, VLD2011-130, pp. 61-66, March 2012. |
Paper # |
VLD2011-130 |
Date of Issue |
2012-02-28 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2011-130 |
Conference Information |
Committee |
VLD |
Conference Date |
2012-03-06 - 2012-03-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
B-con Plaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Methodologies for System-on-a-chip |
Paper Information |
Registration To |
VLD |
Conference Code |
2012-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools |
Sub Title (in English) |
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Keyword(1) |
register transfer level false path |
Keyword(2) |
logic synthesis |
Keyword(3) |
logic optimization |
Keyword(4) |
false path selection |
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1st Author's Name |
Takehiro Mikami |
1st Author's Affiliation |
Hiroshima City University (Hiroshima City Univ.) |
2nd Author's Name |
Tsuyoshi Iwagaki |
2nd Author's Affiliation |
Hiroshima City University (Hiroshima City Univ.) |
3rd Author's Name |
Hideyuki Ichihara |
3rd Author's Affiliation |
Hiroshima City University (Hiroshima City Univ.) |
4th Author's Name |
Tomoo Inoue |
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Hiroshima City University (Hiroshima City Univ.) |
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Speaker |
Author-1 |
Date Time |
2012-03-06 15:55:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2011-130 |
Volume (vol) |
vol.111 |
Number (no) |
no.450 |
Page |
pp.61-66 |
#Pages |
6 |
Date of Issue |
2012-02-28 (VLD) |
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