Paper Abstract and Keywords |
Presentation |
2012-03-06 10:35
Performance evaluation and Improvement of Via Programmable Logic VPEX Taku Otani, Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2011-121 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We have been studying via programmable structured ASIC architecture “VPEX” which can realize arbitrary logic by customizing via layer. The area-delay product of VPEX is estimated as twice of standard-cell based ASIC. In this paper, the area and delay performance of VPEX are compared with other structured ASIC architecture VCLB (Via-Configurable Logic Block) which was proposed by H.H. Tuan in Yuan-Ze University. The evaluated results show that the circuit area of VPEX is less than half that of VCLB, when the identical benchmark circuits are composed on the same delay-performance conditions. However, the delay time of VPEX cannot be decreased even if logic synthesis is performed on smaller timing constraints. We prepared the test library in which some cell with high drivability is added, then some experiments for high speed performance are examined. In addition, we estimated power consumption of VPEX by SPICE simulator. The power consumption of VPEX is 2-4 times as large as that of ASIC when some adders and counters are evaluated. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Via Programmable / structured ASIC / Exclusive-OR / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 450, VLD2011-121, pp. 7-12, March 2012. |
Paper # |
VLD2011-121 |
Date of Issue |
2012-02-28 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2011-121 |
Conference Information |
Committee |
VLD |
Conference Date |
2012-03-06 - 2012-03-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
B-con Plaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Methodologies for System-on-a-chip |
Paper Information |
Registration To |
VLD |
Conference Code |
2012-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Performance evaluation and Improvement of Via Programmable Logic VPEX |
Sub Title (in English) |
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Keyword(1) |
Via Programmable |
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structured ASIC |
Keyword(3) |
Exclusive-OR |
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1st Author's Name |
Taku Otani |
1st Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
2nd Author's Name |
Ryohei Hori |
2nd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
3rd Author's Name |
Tatsuya Kitamori |
3rd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
4th Author's Name |
Taisuke Ueoka |
4th Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
5th Author's Name |
Masaya Yoshikawa |
5th Author's Affiliation |
Meijo University (Meijo Univ.) |
6th Author's Name |
Takeshi Fujino |
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Ritsumeikan University (Ritsumeikan Univ.) |
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Speaker |
Author-1 |
Date Time |
2012-03-06 10:35:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2011-121 |
Volume (vol) |
vol.111 |
Number (no) |
no.450 |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2012-02-28 (VLD) |
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