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| Presentation | 2012-03-06 15:30 CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis Shinji Ohno (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)  VLD2011-129 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, circuit design in languages with higher abstraction level has been widely noticed to address the problem of design productivity crisis. The process transforming these high-level descriptions to conventional RTL description is called high-level synthesis. In this report, we propose two contro-data-flow graph (CDFG) transforming methods based on speculation exploiting implicit parallelism which conventional methods could not find. We applied these two proposed method to benchmark circuit descriptions, and obtained results that proposed methods can shorten executing time of the synthesized circuit. From those results, we confirmed that our methods are effective. Therefore, we can conclude that exploiting the implicit parallelism is useful for behavioral synthesis to generate high-performance circuits. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | high-level synthesis / speculation / control-data-flow graph / parallelization / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 450, VLD2011-129, pp. 55-60, March 2012. | |
| Paper # | VLD2011-129 | |
| Date of Issue | 2012-02-28 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2011-129 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2012-03-06 - 2012-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-con Plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Methodologies for System-on-a-chip |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2012-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | speculation |
| Keyword(3) | control-data-flow graph |
| Keyword(4) | parallelization |
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| 1st Author's Name | Shinji Ohno |
| 1st Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 2nd Author's Name | Kazuyoshi Takagi |
| 2nd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 3rd Author's Name | Naofumi Takagi |
| 3rd Author's Affiliation | Kyoto University (Kyoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2012-03-06 15:30:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2011-129 |
| Volume (vol) | vol.111 |
| Number (no) | no.450 |
| Page | pp.55-60 |
| #Pages | 6 |
| Date of Issue | 2012-02-28 (VLD) |
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