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| Presentation | 2012-03-08 13:45 Hardware Model of Two-Dimensional Non-separable GenLOT for Video Processing Shintaro Hara, Yuya Ota, Shogo Muramatsu (Niigata Univ.)  CAS2011-114 SIP2011-134 CS2011-106 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this report, a hardware model of two-dimensional non-separable GenLOT for video processing and a permutation module for wavelet structure are proposed. Existing transforms such as the discrete cosine trnsform (DCT) and discrete wavelet transform (DWT) are not suitable for the expression of diagonal edges or textures because these transforms are separable. The directional GenLOT proposed in this laboratory is suitable for the expression because it is non-separable. However, there is a problem of the processing speed in the directional GenLOT. It is expected that the specific hardware is effective to solve this problem. Therefore, the authors proposed a hardware model of two-dimensional non-separable GenLOT, where the model is designed for a still image processing. This study suggests to extend the hardware model to video processing of two-dimensional non-separable GenLOT by the modifying the preceding model. In addition, a module for wavelet structure is also proposed. Finally, a part of the model is described by VHDL, and the speed and area are evaluated in order to show the significance of the proposed architecture. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Non-separable GenLOT / DCT / DWT / FPGA / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 466, SIP2011-134, pp. 43-48, March 2012. | |
| Paper # | SIP2011-134 | |
| Date of Issue | 2012-03-01 (CAS, SIP, CS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2011-114 SIP2011-134 CS2011-106 |
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| Conference Information | |
| Committee | CAS CS SIP |
| Conference Date | 2012-03-08 - 2012-03-09 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | The University of Niigata |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Network Processor, Signal Processing for communication, and Wireless LAN/PAN, etc. |
| Paper Information | |
| Registration To | SIP |
| Conference Code | 2012-03-CAS-CS-SIP |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Model of Two-Dimensional Non-separable GenLOT for Video Processing |
| Sub Title (in English) | |
| Keyword(1) | Non-separable GenLOT |
| Keyword(2) | DCT |
| Keyword(3) | DWT |
| Keyword(4) | FPGA |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Shintaro Hara |
| 1st Author's Affiliation | Niigata University (Niigata Univ.) |
| 2nd Author's Name | Yuya Ota |
| 2nd Author's Affiliation | Niigata University (Niigata Univ.) |
| 3rd Author's Name | Shogo Muramatsu |
| 3rd Author's Affiliation | Niigata University (Niigata Univ.) |
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| Speaker | Author-1 |
| Date Time | 2012-03-08 13:45:00 |
| Presentation Time | 25 minutes |
| Registration for | SIP |
| Paper # | CAS2011-114, SIP2011-134, CS2011-106 |
| Volume (vol) | vol.111 |
| Number (no) | no.465(CAS), no.466(SIP), no.467(CS) |
| Page | pp.43-48 |
| #Pages | 6 |
| Date of Issue | 2012-03-01 (CAS, SIP, CS) |
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