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| Presentation | 2012-05-29 10:35 A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array Toru Katagiri, Kazuei Hironaka, Hideharu Amano (Keio Univ.)  RECONF2012-4 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use PEs effectively. However, a prototype DRPA, MuCCRA-3 needs to generate read/write addresses for accessing data memories, and counts a number of loops on PEs. Hence, PEs of MuCCRA-3 can not be used effectively for actual processing of applications. To solve this problem and improve performance. We extend the memory controller of MuCCRA-3 and named it MuCCRA-3-EXMC. PEs of MuCCRA-3-EXMC can be concentrated on executing the actual processing by the extended memory controller performing address generation and loop count. Evaluation results showed that MuCCRA-3-EXMC can improve its performance by 12-23% and reduce its energy consumption by 9-20% without a large increase of its area. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Dynamically Reconfigurable Processor Array / Accelerator / Memory Controller / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 70, RECONF2012-4, pp. 19-24, May 2012. | |
| Paper # | RECONF2012-4 | |
| Date of Issue | 2012-05-22 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Notes on Review | This article is a technical report without peer review, and its polished version will be published elsewhere. | |
| Download PDF | RECONF2012-4 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2012-05-29 - 2012-05-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tiruru (Naha Okinawa, Japan) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2012-05-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable Processor Array |
| Keyword(2) | Accelerator |
| Keyword(3) | Memory Controller |
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| 1st Author's Name | Toru Katagiri |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Kazuei Hironaka |
| 2nd Author's Affiliation | Keio University (Keio Univ.) |
| 3rd Author's Name | Hideharu Amano |
| 3rd Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2012-05-29 10:35:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2012-4 |
| Volume (vol) | vol.112 |
| Number (no) | no.70 |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2012-05-22 (RECONF) |
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