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Paper Abstract and Keywords
Presentation 2012-06-14 11:20
High-Speed and Low-Power Design of a Singular Value Decomposition Processor for SVD-MIMO-OFDM Systems
Hiroki Iwaizumi (HU), Shingo Yoshizawa (KIT), Yoshikazu Miyanaga (HU) SIS2012-3
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a processor for singular value decomposition (SVD) and compression/reconstruction of feedback matrix, which is mandatory for SVD - multiple-input multiple-output - orthogonal frequency division multiplexing(MIMO-OFDM) systems. The SVD-MIMO is a transmission method, which can suppress multi-stream interference and improve communication quality by beamforming. Because of high calculation cost, any conventional SVD processors are unsuitable for real-time processing. We have employed an application specific instruction-set processor(ASIP) architecture and have realized the high-speed/low-power design and real-time processing by the parallelization of floating point unit(FPU) and arithmetic instructions specialized in complex matrix operations.
Keyword (in Japanese) (See Japanese page) 
(in English) SVD-MIMO / Singular value decomposition / ASIP / FPU / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 78, SIS2012-3, pp. 13-18, June 2012.
Paper # SIS2012-3 
Date of Issue 2012-06-07 (SIS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SIS  
Conference Date 2012-06-14 - 2012-06-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Tokachi Plaza (Obihiro City) 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SIS 
Conference Code 2012-06-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) High-Speed and Low-Power Design of a Singular Value Decomposition Processor for SVD-MIMO-OFDM Systems 
Sub Title (in English)  
Keyword(1) SVD-MIMO  
Keyword(2) Singular value decomposition  
Keyword(3) ASIP  
Keyword(4) FPU  
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1st Author's Name Hiroki Iwaizumi  
1st Author's Affiliation Hokkaido University (HU)
2nd Author's Name Shingo Yoshizawa  
2nd Author's Affiliation Kitami Institute of Technology (KIT)
3rd Author's Name Yoshikazu Miyanaga  
3rd Author's Affiliation Hokkaido University (HU)
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Speaker Author-1 
Date Time 2012-06-14 11:20:00 
Presentation Time 25 minutes 
Registration for SIS 
Paper # SIS2012-3 
Volume (vol) vol.112 
Number (no) no.78 
Page pp.13-18 
#Pages
Date of Issue 2012-06-07 (SIS) 


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