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| Presentation | 2012-06-22 14:20 [Invited Talk] Empirical study for signal integrity-defects Hiroshi Takahashi, Yoshinobu Higami (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. Tokushima)  DC2012-12 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We try to empirically study signal integrity-defects. In this study, we analyze the resistive open fault that causes the signal integrity-defect by using the three-dimensional (3-D) electromagnetic software and the TEG with the resistive open faults.We propose a method for generating the test patterns for the resistive open faults under the launch-off-capture (LOC) test.We also propose a method for diagnosing the resistive open faults by using the diagnostic delay fault simulation with considering the affects of the adjacent lines. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | resistive open fault / test pattern generation / diagnosis / extended delay fault model / adjacent lines / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 102, DC2012-12, pp. 21-26, June 2012. | |
| Paper # | DC2012-12 | |
| Date of Issue | 2012-06-15 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2012-12 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2012-06-22 - 2012-06-22 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Room B3-1 Kikai-Shinko-Kaikan Bldg |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design, Test, Verification |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2012-06-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Empirical study for signal integrity-defects |
| Sub Title (in English) | |
| Keyword(1) | resistive open fault |
| Keyword(2) | test pattern generation |
| Keyword(3) | diagnosis |
| Keyword(4) | extended delay fault model |
| Keyword(5) | adjacent lines |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hiroshi Takahashi |
| 1st Author's Affiliation | Ehime University (Ehime Univ.) |
| 2nd Author's Name | Yoshinobu Higami |
| 2nd Author's Affiliation | Ehime University (Ehime Univ.) |
| 3rd Author's Name | Toshiyuki Tsutsumi |
| 3rd Author's Affiliation | Meiji University (Meiji Univ.) |
| 4th Author's Name | Koji Yamazaki |
| 4th Author's Affiliation | Meiji University (Meiji Univ.) |
| 5th Author's Name | Hiroyuki Yotsuyanagi |
| 5th Author's Affiliation | University of Tokushima (Univ. Tokushima) |
| 6th Author's Name | Masaki Hashizume |
| 6th Author's Affiliation | University of Tokushima (Univ. Tokushima) |
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| Speaker | Author-1 |
| Date Time | 2012-06-22 14:20:00 |
| Presentation Time | 50 minutes |
| Registration for | DC |
| Paper # | DC2012-12 |
| Volume (vol) | vol.112 |
| Number (no) | no.102 |
| Page | pp.21-26 |
| #Pages | 6 |
| Date of Issue | 2012-06-15 (DC) |
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