IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2012-06-28 10:40
[Poster Presentation] Rigorous Design for Gate-Dielectric and n-Pocket Region of Tunneling Field-Effect Transistors and Its High Performances.
Jae Hwa Seo, Jae Sung Lee, Yun Soo Park, Jung-Hee Lee, In Man Kang (Kyunpook Nat'l Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) A gate-all-around tunneling field-effect transistor (GAA TFET) with high-k gate-dielectric and n-pocket layer is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-pocket layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) and n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off- current (Ion and Ioff), subthreshold swing (SS), and RF performances.
Keyword (in Japanese) (See Japanese page) 
(in English) gate-all-around (GAA) / tunneling field-effect transistor (TFET) / n-pocket layer / / / / /  
Reference Info. IEICE Tech. Rep.
Paper #  
Date of Issue  
ISSN  
Download PDF

Conference Information
Committee SDM ED  
Conference Date 2012-06-27 - 2012-06-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen-kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) 2012 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices 
Paper Information
Registration To SDM 
Conference Code 2012-06-SDM-ED 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Rigorous Design for Gate-Dielectric and n-Pocket Region of Tunneling Field-Effect Transistors and Its High Performances. 
Sub Title (in English)  
Keyword(1) gate-all-around (GAA)  
Keyword(2) tunneling field-effect transistor (TFET)  
Keyword(3) n-pocket layer  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Jae Hwa Seo  
1st Author's Affiliation Kyungpook National University (Kyunpook Nat'l Univ.)
2nd Author's Name Jae Sung Lee  
2nd Author's Affiliation Kyungpook National University (Kyunpook Nat'l Univ.)
3rd Author's Name Yun Soo Park  
3rd Author's Affiliation Kyungpook National University (Kyunpook Nat'l Univ.)
4th Author's Name Jung-Hee Lee  
4th Author's Affiliation Kyungpook National University (Kyunpook Nat'l Univ.)
5th Author's Name In Man Kang  
5th Author's Affiliation Kyungpook National University (Kyunpook Nat'l Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2012-06-28 10:40:00 
Presentation Time 80 minutes 
Registration for SDM 
Paper #  
Volume (vol) vol. 
Number (no)  
Page  
#Pages  
Date of Issue  

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan