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| Presentation | 2012-09-20 10:40 A High-Performance Multiplierless Hardware Architecture of the Transform Applied to H.265/HEVC Emerging Video Coding Standard Wenjun Zhao, Takao Onoye (Osaka Univ.)  SIS2012-18 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper presents a hardware architecture of the transform applied in the emerging video coding standard-HEVC (High Efficiency Video Coding). The transform coding tool is one of the innovational feature adopted by HEVC, because of the variable transform matrix size (from 4x4 to 32x32), while the traditional transform size is 4x4 and 8x8 used by the H.264/AVC. The hardware design proposed in this paper focuses on low cost and high throughput. To obtain such objectives, some simplification strategies were adopted during the implementation, such as reusing part of larger size transform structure by smaller size, and turning multiplications by constant into shift and sum operations. Moreover, the transform architecture proposed in this paper was implemented in the form of pipeline structure. The designed architecture was described using Verilog HDL, and synthesis on an Altera Cyclone IV E FPGA. The results showed that the design achieved a maximum operation frequency of 114.29 MHz, and can process 190.50Msamples/s on average, allowing it to process Class A video se-quences (2560x1600 pixels, 30fps) and Full HD sequences (1920x1080 pixels, 60fps). Therefore, the proposed architecture is capable to processing video sequences with high definition in real time. To the best of our knowledge, this is the first work in the literature that presents fully hardware results on FPGA platform for the HEVC transforms with a variable size from 4x4 to 32x32. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | HEVC / Transform / Hardware architecture / Pipeline structure / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 207, SIS2012-18, pp. 11-16, Sept. 2012. | |
| Paper # | SIS2012-18 | |
| Date of Issue | 2012-09-13 (SIS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SIS2012-18 |
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| Conference Information | |
| Committee | SIS IPSJ-AVM |
| Conference Date | 2012-09-20 - 2012-09-21 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tottori Pref. Osaka Office |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | SIS |
| Conference Code | 2012-09-SIS-AVM |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A High-Performance Multiplierless Hardware Architecture of the Transform Applied to H.265/HEVC Emerging Video Coding Standard |
| Sub Title (in English) | |
| Keyword(1) | HEVC |
| Keyword(2) | Transform |
| Keyword(3) | Hardware architecture |
| Keyword(4) | Pipeline structure |
| Keyword(5) | |
| Keyword(6) | |
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| 1st Author's Name | Wenjun Zhao |
| 1st Author's Affiliation | Osaka University (Osaka Univ.) |
| 2nd Author's Name | Takao Onoye |
| 2nd Author's Affiliation | Osaka University (Osaka Univ.) |
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| Speaker | Author-1 |
| Date Time | 2012-09-20 10:40:00 |
| Presentation Time | 25 minutes |
| Registration for | SIS |
| Paper # | SIS2012-18 |
| Volume (vol) | vol.112 |
| Number (no) | no.207 |
| Page | pp.11-16 |
| #Pages | 6 |
| Date of Issue | 2012-09-13 (SIS) |
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