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| Presentation | 2012-11-27 13:50 Energy-efficient High-level Synthesis Considering Clock Design for HDR Architectures Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2012-81 DC2012-47 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With the miniaturization of LSIs and its increasing performance, demand for high-functional portable devices has grown significantly. At the same time, the problems for battery runtime and device overheating have occurred. On the other hand, the ratio of an interconnection delay to a gate delay has continued to increase as device feature size decreases. We have to estimate the interconnection delay and reduce energy consumption even in a high-level synthesis stage. In this paper, we propose high-level synthesis considering clock design for HDR architectures with concurrency-oriented scheduling. Firstly we focus on the number of the control steps at which we can apply the clock gating to registers and we schedule and bind operations to be performed at the same time. By adjusting the clock gating timings in a high-level synthesis stage, we enhance the effect of clock gatings than applying clock gatings after logic synthesis. Secondly, we determine the clock gating timings to minimize all energy consumption including clock tree energy. The experimental results show that our proposed algorithm reduces energy consumption by a maximum of 21.2% compared with several conventionalalgorithms. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | HDR / concurrency-oriented scheduling / clock tree / clock gating timings / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 320, VLD2012-81, pp. 129-134, Nov. 2012. | |
| Paper # | VLD2012-81 | |
| Date of Issue | 2012-11-19 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-81 DC2012-47 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2012-11-26 - 2012-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Centennial Hall Kyushu University School of Medicine |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2012 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Energy-efficient High-level Synthesis Considering Clock Design for HDR Architectures |
| Sub Title (in English) | |
| Keyword(1) | HDR |
| Keyword(2) | concurrency-oriented scheduling |
| Keyword(3) | clock tree |
| Keyword(4) | clock gating timings |
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| Keyword(6) | |
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| Keyword(8) | |
| 1st Author's Name | Hiroyuki Akasaka |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Masao Yanagisawa |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Nozomu Togawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2012-11-27 13:50:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2012-81, DC2012-47 |
| Volume (vol) | vol.112 |
| Number (no) | no.320(VLD), no.321(DC) |
| Page | pp.129-134 |
| #Pages | 6 |
| Date of Issue | 2012-11-19 (VLD, DC) |
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