Paper Abstract and Keywords |
Presentation |
2012-11-28 10:55
AES Cryptographic Circuit utilizing Dual-Rail RSL Memory Technique Yuki Hashimoto, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino (Ritsumeikan Univ.) CPM2012-120 ICD2012-84 Link to ES Tech. Rep. Archives: CPM2012-120 ICD2012-84 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Tamper LSI design methodology has to be applied in order to implement secure cryptographic circuit, which is resistant to side-channel attacks such as PA (Power Analysis). We have proposed the PA-resistant countermeasure called the “dual-rail RSL memory”. On the cryptographic circuit using this scheme, the dual-rail complementary approach is used to consume constant power regardless of input/output values. And, the masking technique is used to hide correlations between the secret key and the power consumptions. A prototype AES chip was designed and fabricated with a 0.18μm CMOS technology. The circuit area and the power consumption during one encryption operation are 900,191 um2 and 22.24 nJ, respectively, and the proposed scheme achieves low area and low power compared with other countermeasures. In addition, the number of traces in order to disclose all secret byte keys is over 106, and the sufficient resistance against PA is demonstrated in the experimental results. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Side-Channel Attack / AES / DPA / CPA / Dual-Rail RSL Memory / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 324, ICD2012-84, pp. 43-48, Nov. 2012. |
Paper # |
ICD2012-84 |
Date of Issue |
2012-11-20 (CPM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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CPM2012-120 ICD2012-84 Link to ES Tech. Rep. Archives: CPM2012-120 ICD2012-84 |
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