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Paper Abstract and Keywords
Presentation 2012-11-28 10:55
AES Cryptographic Circuit utilizing Dual-Rail RSL Memory Technique
Yuki Hashimoto, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino (Ritsumeikan Univ.) CPM2012-120 ICD2012-84 Link to ES Tech. Rep. Archives: CPM2012-120 ICD2012-84
Abstract (in Japanese) (See Japanese page) 
(in English) Tamper LSI design methodology has to be applied in order to implement secure cryptographic circuit, which is resistant to side-channel attacks such as PA (Power Analysis). We have proposed the PA-resistant countermeasure called the “dual-rail RSL memory”. On the cryptographic circuit using this scheme, the dual-rail complementary approach is used to consume constant power regardless of input/output values. And, the masking technique is used to hide correlations between the secret key and the power consumptions. A prototype AES chip was designed and fabricated with a 0.18μm CMOS technology. The circuit area and the power consumption during one encryption operation are 900,191 um2 and 22.24 nJ, respectively, and the proposed scheme achieves low area and low power compared with other countermeasures. In addition, the number of traces in order to disclose all secret byte keys is over 106, and the sufficient resistance against PA is demonstrated in the experimental results.
Keyword (in Japanese) (See Japanese page) 
(in English) Side-Channel Attack / AES / DPA / CPA / Dual-Rail RSL Memory / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 324, ICD2012-84, pp. 43-48, Nov. 2012.
Paper # ICD2012-84 
Date of Issue 2012-11-20 (CPM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPM2012-120 ICD2012-84 Link to ES Tech. Rep. Archives: CPM2012-120 ICD2012-84

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2012-11-26 - 2012-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Centennial Hall Kyushu University School of Medicine 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2012 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) AES Cryptographic Circuit utilizing Dual-Rail RSL Memory Technique 
Sub Title (in English)  
Keyword(1) Side-Channel Attack  
Keyword(2) AES  
Keyword(3) DPA  
Keyword(4) CPA  
Keyword(5) Dual-Rail RSL Memory  
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1st Author's Name Yuki Hashimoto  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Mitsuru Shiozaki  
2nd Author's Affiliation Research Organization of Science and Engineering, Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name Takaya Kubota  
3rd Author's Affiliation Research Organization of Science and Engineering, Ritsumeikan University (Ritsumeikan Univ.)
4th Author's Name Takeshi Fujino  
4th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
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Speaker Author-1 
Date Time 2012-11-28 10:55:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # CPM2012-120, ICD2012-84 
Volume (vol) vol.112 
Number (no) no.323(CPM), no.324(ICD) 
Page pp.43-48 
#Pages
Date of Issue 2012-11-20 (CPM, ICD) 


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