Paper Abstract and Keywords |
Presentation |
2012-11-28 10:30
A LSI-Package-Board co-evaluation of Power noise in the Digital LSI Kumpei Yoshikawa, Yuta Sasaki (Kobe Univ.), Kouji Ichikawa (DENSO), Yoshiyuki Saito (Panasonic), Makoto Nagata (Kobe Univ.) VLD2012-91 DC2012-57 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Problems related with power noise in LSI system are getting prominent
because of the higher integration and lower $V_{dd}$ voltage of an LSI chip.
A Power noise simulation method that could use in various design phases is required for designing noise-tolerant and low-cost systems.
The impedance profile of power delivery network(PDN) and circuit operations strongly affects the power noise characteristics.
The simulation model that contains whole elements of system such as LSIs, packages, and boards is required.
In this paper, we present the LSI-package-board combined power noise simulation model.
Accuracy of the simulation model is confirmed by comparing the on-chip noise meaurement results using an on-chip noise monitor circuit and on-board noise measurement results using a magnetic probe method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Power noise / Power integrity / EMC / Noise simulation / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 320, VLD2012-91, pp. 183-188, Nov. 2012. |
Paper # |
VLD2012-91 |
Date of Issue |
2012-11-19 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2012-91 DC2012-57 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2012-11-26 - 2012-11-28 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Centennial Hall Kyushu University School of Medicine |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2012 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A LSI-Package-Board co-evaluation of Power noise in the Digital LSI |
Sub Title (in English) |
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Keyword(1) |
Power noise |
Keyword(2) |
Power integrity |
Keyword(3) |
EMC |
Keyword(4) |
Noise simulation |
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1st Author's Name |
Kumpei Yoshikawa |
1st Author's Affiliation |
Kobe University (Kobe Univ.) |
2nd Author's Name |
Yuta Sasaki |
2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
3rd Author's Name |
Kouji Ichikawa |
3rd Author's Affiliation |
DENSO CORPORATION (DENSO) |
4th Author's Name |
Yoshiyuki Saito |
4th Author's Affiliation |
Panasonic Corporation (Panasonic) |
5th Author's Name |
Makoto Nagata |
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Kobe University (Kobe Univ.) |
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Speaker |
Author-1 |
Date Time |
2012-11-28 10:30:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2012-91, DC2012-57 |
Volume (vol) |
vol.112 |
Number (no) |
no.320(VLD), no.321(DC) |
Page |
pp.183-188 |
#Pages |
6 |
Date of Issue |
2012-11-19 (VLD, DC) |
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