Paper Abstract and Keywords |
Presentation |
2013-01-16 09:10
Architecture Evaluation of a Reconfigurable Device MPLD Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) VLD2012-107 CPSY2012-56 RECONF2012-61 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we discuss the detailed structure of MPLD, an architecture for
realizing reconfigurable devices. MPLD consists of small memories connected by
pairs of address and data lines (AD pairs). These memories, called MLUTs, are
used as LUTs to realize logic cells, and also switch blocks to realize wires
between the logic cells. Thus, the number of AD pairs per MLUT and the
connection pattern among MLUTs by AD pairs greatly affect the performance and
acceptable size of circuits mapped to the MPLD. Therefore, we compare a variety
of MPLD architectures, which have the different numbers of AD pairs per MLUT and
the different connection patterns among MLUTs, in some metrics. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
MPLD / PLD / FPGA / architecture / Place-and-Route / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 377, RECONF2012-61, pp. 1-6, Jan. 2013. |
Paper # |
RECONF2012-61 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2012-107 CPSY2012-56 RECONF2012-61 |
Conference Information |
Committee |
CPSY VLD RECONF IPSJ-SLDM |
Conference Date |
2013-01-16 - 2013-01-17 |
Place (in Japanese) |
(See Japanese page) |
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Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
RECONF |
Conference Code |
2013-01-CPSY-VLD-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Architecture Evaluation of a Reconfigurable Device MPLD |
Sub Title (in English) |
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Keyword(1) |
MPLD |
Keyword(2) |
PLD |
Keyword(3) |
FPGA |
Keyword(4) |
architecture |
Keyword(5) |
Place-and-Route |
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1st Author's Name |
Tomoya Yamashita |
1st Author's Affiliation |
Hiroshima City University (Hiroshima City Univ) |
2nd Author's Name |
Masato Inagi |
2nd Author's Affiliation |
Hiroshima City University (Hiroshima City Univ) |
3rd Author's Name |
Kazuya Tanigawa |
3rd Author's Affiliation |
Hiroshima City University (Hiroshima City Univ) |
4th Author's Name |
Tetsuo Hironaka |
4th Author's Affiliation |
Hiroshima City University (Hiroshima City Univ) |
5th Author's Name |
Takashi Ishiguro |
5th Author's Affiliation |
TAIYO YUDEN CO.LTD (TAIYO YUDEN) |
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Speaker |
Author-1 |
Date Time |
2013-01-16 09:10:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
VLD2012-107, CPSY2012-56, RECONF2012-61 |
Volume (vol) |
vol.112 |
Number (no) |
no.375(VLD), no.376(CPSY), no.377(RECONF) |
Page |
pp.1-6 |
#Pages |
6 |
Date of Issue |
2013-01-09 (VLD, CPSY, RECONF) |
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