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| Presentation | 2013-01-17 13:25 A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.)  VLD2012-130 CPSY2012-79 RECONF2012-84 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow of execution run on CPU and reconfigurable hardware. This paper presents a channel-based communication model tailored for such systems. The channels are abstract objects with unique and statically assigned IDs, passed as a parameter to channel access API calls. Physically, they are divided into master and slave parts located either in SW or dynamically reconfigured with the HW task, which allows for point-to-point inter-task communication, its optimizations between a given pair of tasks and decreases the overall logic utilization in the system. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SW-HW Multitasking / Dynamic Reconfiguration / Runtime Reconfiguration / FPGA / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 377, RECONF2012-84, pp. 135-140, Jan. 2013. | |
| Paper # | RECONF2012-84 | |
| Date of Issue | 2013-01-09 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-130 CPSY2012-79 RECONF2012-84 |
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| Conference Information | |
| Committee | CPSY VLD RECONF IPSJ-SLDM |
| Conference Date | 2013-01-16 - 2013-01-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2013-01-CPSY-VLD-RECONF-SLDM |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs |
| Sub Title (in English) | |
| Keyword(1) | SW-HW Multitasking |
| Keyword(2) | Dynamic Reconfiguration |
| Keyword(3) | Runtime Reconfiguration |
| Keyword(4) | FPGA |
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| 1st Author's Name | Krzysztof Jozwik |
| 1st Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 2nd Author's Name | Shinya Honda |
| 2nd Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 3rd Author's Name | Masato Edahiro |
| 3rd Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 4th Author's Name | Hiroyuki Tomiyama |
| 4th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 5th Author's Name | Hiroaki Takada |
| 5th Author's Affiliation | Nagoya University (Nagoya Univ.) |
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| Speaker | Author-1 |
| Date Time | 2013-01-17 13:25:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2012-130, CPSY2012-79, RECONF2012-84 |
| Volume (vol) | vol.112 |
| Number (no) | no.375(VLD), no.376(CPSY), no.377(RECONF) |
| Page | pp.135-140 |
| #Pages | 6 |
| Date of Issue | 2013-01-09 (VLD, CPSY, RECONF) |
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