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| Presentation | 2013-01-24 17:20 Design of a threshold-coupled CMOS chaos circuit using voltage/current waveform sampling Seiji Uenohara, Daisuke Atuti, Kenji Matsuzaka, Takashi Morie (Kyutech), Kazuyuki Aihara (Univ. of Tokyo)  NLP2012-122 NC2012-112 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In order to develop large-scale coupled nonlinear dynamical systems using CMOS integrated circuits, we propose a threshold-coupled map array circuit that is robust to CMOS device mismatch. We have already proposed a voltage- and a current-sampling mode circuits which can achieve arbitrary analog nonlinear dynamics in the time domain by using pulse width/phase modulation (PWM/PPM) signals. Both circuits have advantages of robustness to parameter mismatches of CMOS circuit elements and facilitation of weighted summation of connected states, respectively. These advantages are important for developing a large-scale coupled array circuit. In this study, we employ a circuit architecture having the advantages of these sampling mode, and propose a circuit that is robust to voltage-shift dispersion of CMOS analog buffers. We show this robustness of the proposed circuit by SPICE circuit simulation. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | CMOS integrated circuit / large-scale coupled system / voltage/current-sampling mode / PWM / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 389, NLP2012-122, pp. 105-110, Jan. 2013. | |
| Paper # | NLP2012-122 | |
| Date of Issue | 2013-01-17 (NLP, NC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | NLP2012-122 NC2012-112 |
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| Conference Information | |
| Committee | NC NLP |
| Conference Date | 2013-01-24 - 2013-01-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido University Centennial Memory Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | NLP |
| Conference Code | 2013-01-NC-NLP |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of a threshold-coupled CMOS chaos circuit using voltage/current waveform sampling |
| Sub Title (in English) | |
| Keyword(1) | CMOS integrated circuit |
| Keyword(2) | large-scale coupled system |
| Keyword(3) | voltage/current-sampling mode |
| Keyword(4) | PWM |
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| 1st Author's Name | Seiji Uenohara |
| 1st Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 2nd Author's Name | Daisuke Atuti |
| 2nd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 3rd Author's Name | Kenji Matsuzaka |
| 3rd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 4th Author's Name | Takashi Morie |
| 4th Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 5th Author's Name | Kazuyuki Aihara |
| 5th Author's Affiliation | The University of Tokyo (Univ. of Tokyo) |
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| Speaker | Author-1 |
| Date Time | 2013-01-24 17:20:00 |
| Presentation Time | 20 minutes |
| Registration for | NLP |
| Paper # | NLP2012-122, NC2012-112 |
| Volume (vol) | vol.112 |
| Number (no) | no.389(NLP), no.390(NC) |
| Page | pp.105-110 |
| #Pages | 6 |
| Date of Issue | 2013-01-17 (NLP, NC) |
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