Paper Abstract and Keywords |
Presentation |
2013-01-25 14:10
Development of a Spiking Neural Network System Consisting of a Dedicated Analog LSI Chip Controlled by an FPGA Michitaka Maeda, Frank Maldonado H., Takayuki Matsuo, Hideki Tanaka, Haichao Liang, Kenji Matsuzaka, Takashi Morie (Kyutech), Kazuyuki Aihara (Univ. of Tokyo) NLP2012-136 NC2012-126 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Spiking neuron models, in which analog information is expressed by the timing of neuronal spike firing events, attract a great deal of attention. We have already proposed an analog CMOS circuit of the integrate-and-fire spiking neuron model with spike-timing dependent synaptic plasticity (STDP), and have designed and fabricated a CMOS LSI spiking neural network chip. We have demonstrated associative memory operation of a Hopfield-type spiking neural network with memorization of patterns using symmetric STDP by chip measurements. In this paper, we describe a developed spiking neural network system including this dedicated LSI chip controlled by an FPGA, and show experimental results using our system. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Spiking neuron model / Spike-timing dependent synaptic plasticity (STDP) / Analog CMOS LSI / FPGA / Neural system / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 390, NC2012-126, pp. 181-186, Jan. 2013. |
Paper # |
NC2012-126 |
Date of Issue |
2013-01-17 (NLP, NC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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NLP2012-136 NC2012-126 |
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