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Paper Abstract and Keywords
Presentation 2013-01-25 14:10
Development of a Spiking Neural Network System Consisting of a Dedicated Analog LSI Chip Controlled by an FPGA
Michitaka Maeda, Frank Maldonado H., Takayuki Matsuo, Hideki Tanaka, Haichao Liang, Kenji Matsuzaka, Takashi Morie (Kyutech), Kazuyuki Aihara (Univ. of Tokyo) NLP2012-136 NC2012-126
Abstract (in Japanese) (See Japanese page) 
(in English) Spiking neuron models, in which analog information is expressed by the timing of neuronal spike firing events, attract a great deal of attention. We have already proposed an analog CMOS circuit of the integrate-and- fire spiking neuron model with spike-timing dependent synaptic plasticity (STDP), and have designed and fabricated a CMOS LSI spiking neural network chip. We have demonstrated associative memory operation of a Hopfi eld-type spiking neural network with memorization of patterns using symmetric STDP by chip measurements. In this paper, we describe a developed spiking neural network system including this dedicated LSI chip controlled by an FPGA, and show experimental results using our system.
Keyword (in Japanese) (See Japanese page) 
(in English) Spiking neuron model / Spike-timing dependent synaptic plasticity (STDP) / Analog CMOS LSI / FPGA / Neural system / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 390, NC2012-126, pp. 181-186, Jan. 2013.
Paper # NC2012-126 
Date of Issue 2013-01-17 (NLP, NC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NLP2012-136 NC2012-126

Conference Information
Committee NC NLP  
Conference Date 2013-01-24 - 2013-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido University Centennial Memory Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To NC 
Conference Code 2013-01-NC-NLP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of a Spiking Neural Network System Consisting of a Dedicated Analog LSI Chip Controlled by an FPGA 
Sub Title (in English)  
Keyword(1) Spiking neuron model  
Keyword(2) Spike-timing dependent synaptic plasticity (STDP)  
Keyword(3) Analog CMOS LSI  
Keyword(4) FPGA  
Keyword(5) Neural system  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Michitaka Maeda  
1st Author's Affiliation Kyushu Institute of Technology (Kyutech)
2nd Author's Name Frank Maldonado H.  
2nd Author's Affiliation Kyushu Institute of Technology (Kyutech)
3rd Author's Name Takayuki Matsuo  
3rd Author's Affiliation Kyushu Institute of Technology (Kyutech)
4th Author's Name Hideki Tanaka  
4th Author's Affiliation Kyushu Institute of Technology (Kyutech)
5th Author's Name Haichao Liang  
5th Author's Affiliation Kyushu Institute of Technology (Kyutech)
6th Author's Name Kenji Matsuzaka  
6th Author's Affiliation Kyushu Institute of Technology (Kyutech)
7th Author's Name Takashi Morie  
7th Author's Affiliation Kyushu Institute of Technology (Kyutech)
8th Author's Name Kazuyuki Aihara  
8th Author's Affiliation The University of Tokyo (Univ. of Tokyo)
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Speaker Author-1 
Date Time 2013-01-25 14:10:00 
Presentation Time 20 minutes 
Registration for NC 
Paper # NLP2012-136, NC2012-126 
Volume (vol) vol.112 
Number (no) no.389(NLP), no.390(NC) 
Page pp.181-186 
#Pages
Date of Issue 2013-01-17 (NLP, NC) 


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