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Paper Abstract and Keywords
Presentation 2013-02-13 15:50
A Method of Acceptable Fault Identification with Necessary Assignment in Logic Simplification for Error Tolerant Application
Shingo Matsuki, Junpei Kamei, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2012-88
Abstract (in Japanese) (See Japanese page) 
(in English) In error tolerant applications, some specific errors, which are of certain types or have severities within certain limits, of LSIs for such applications are tolerable.
In this paper, we focus on logic optimization of circuits for error tolerant applications[10-12].
In the previous method, to identify removable portions of a logic circuit, the acceptability of stuck-at faults in the circuit is checked by
utilizing threshold test generation algorithm, even though this acceptability identification is time-consuming[12].
To accelerate of this acceptability identification, we propose an acceptability identification procedure based on
necessary assignments requires for detecting unacceptable faults. Discussing the relationship between multiple acceptable faults and necessary assignmetns, we present an algorithm, which is faster than the test-generation-based previous algorithm, to check the acceptability of faults with implication procedure.
Experimental results show that the proposed algorithm can reduce the computation effort to identify acceptable faults.
Keyword (in Japanese) (See Japanese page) 
(in English) acceptable faults / logic optimization / error significance / acceptability identification / error tolerance / necessary assignment / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 429, DC2012-88, pp. 49-54, Feb. 2013.
Paper # DC2012-88 
Date of Issue 2013-02-06 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2013-02-13 - 2013-02-13 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2013-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Method of Acceptable Fault Identification with Necessary Assignment in Logic Simplification for Error Tolerant Application 
Sub Title (in English)  
Keyword(1) acceptable faults  
Keyword(2) logic optimization  
Keyword(3) error significance  
Keyword(4) acceptability identification  
Keyword(5) error tolerance  
Keyword(6) necessary assignment  
Keyword(7)  
Keyword(8)  
1st Author's Name Shingo Matsuki  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Junpei Kamei  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Tsuyoshi Iwagaki  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Hideyuki Ichihara  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
5th Author's Name Tomoo Inoue  
5th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2013-02-13 15:50:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2012-88 
Volume (vol) vol.112 
Number (no) no.429 
Page pp.49-54 
#Pages
Date of Issue 2013-02-06 (DC) 


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