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Paper Abstract and Keywords
Presentation 2013-05-18 09:55
Complexity of Counting Output Patterns of Logic Circuits
Kei Uchizawa (Yamagata Univ.), Zhenghong Wang (Tohoku Univ.), Hiroki Morizumi (Shimane Univ.), Xiao Zhou (Tohoku Univ.) COMP2013-14
Abstract (in Japanese) (See Japanese page) 
(in English) Let $C$ be a logic circuit consisting of $s$ gates
$g_1, g_2, dots , g_s$, then
the output pattern of $C$ for an input
$Vec{x} in { 0, 1}^n$ is defined to be a vector
$(g_1(Vec{x}), g_2 (Vec{x}), dots , g_s(Vec{x})) in { 0, 1} ^s$ of the outputs
of $g_1, g_2, dots , g_s$ for $Vec{x}$.
For each $f: { 0, 1} ^2 to {0 ,1}$,
we define an $f$-circuit as a logic circuit where every gate computes $f$, and
investigate computational complexity of the following counting
problem: Given an $f$-circuit $C$, how many
output patterns arise in $C$?
We then provide a dichotomy result on the counting problem:
We prove that the problem is solvable in polynomial time
if $f$ is PARITY or any degenerate function,
while the problem is p-complete even for constant-depth $f$-circuits
if $f$ is one of the other functions, such as
AND, OR, NAND and NOR.
Keyword (in Japanese) (See Japanese page) 
(in English) Boolean functions / counting complexity / logic circuits / minimum AND-circuits problem / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 50, COMP2013-14, pp. 97-102, May 2013.
Paper # COMP2013-14 
Date of Issue 2013-05-10 (COMP) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF COMP2013-14

Conference Information
Committee COMP IPSJ-AL  
Conference Date 2013-05-17 - 2013-05-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Otaru University of Commerce 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To COMP 
Conference Code 2013-05-COMP-AL 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Complexity of Counting Output Patterns of Logic Circuits 
Sub Title (in English)  
Keyword(1) Boolean functions  
Keyword(2) counting complexity  
Keyword(3) logic circuits  
Keyword(4) minimum AND-circuits problem  
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1st Author's Name Kei Uchizawa  
1st Author's Affiliation Yamagata University (Yamagata Univ.)
2nd Author's Name Zhenghong Wang  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Hiroki Morizumi  
3rd Author's Affiliation Shimne University (Shimane Univ.)
4th Author's Name Xiao Zhou  
4th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2013-05-18 09:55:00 
Presentation Time 25 minutes 
Registration for COMP 
Paper # COMP2013-14 
Volume (vol) vol.113 
Number (no) no.50 
Page pp.97-102 
#Pages 6 
Date of Issue 2013-05-10 (COMP) 

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