Paper Abstract and Keywords |
Presentation |
2013-09-19 13:00
The Circuit Configuration method of 3D FPGA-Array System "Vocalise" Hiromasa Kubo, Jiang Li, Yusuke Atsumari, Baku Ogasawara, Masatoshi Sekine (Tokyo Univ. of Agliculture and Tech.) RECONF2013-32 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We have been developing the 3D FPGA-Array HPC system named as“Vocalise(Virtual Object by Configurable Array of Little Scalable Engine)”that is composed of large numbers of the FPGA card which has controller FPGA and processing FPGA. This system has 6 I/O terminals for connecting each other in 3 dimensional formations. Therefore, this system enables to achieve high speed communication among FPGAs in the FPGA arrays. We present communication and cotrol system. Furthermore, we show how to implement image processing circuit within“Vocalise”for the robot. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Vocalise / 3D FPGA-Array / Reconfigurable HPC / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 221, RECONF2013-32, pp. 73-78, Sept. 2013. |
Paper # |
RECONF2013-32 |
Date of Issue |
2013-09-11 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
RECONF2013-32 |