IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2013-11-27 09:15
Co-design for reducing power supply noises with On-die PDN Impedance
Ryota Kobayashi, Hiroki Otsuka, Genki Kubo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Toshio Sudo (Shibaura Inst. of Tech.) CPM2013-109 ICD2013-86 Link to ES Tech. Rep. Archives: CPM2013-109 ICD2013-86
Abstract (in Japanese) (See Japanese page) 
(in English) Power integrity is a serious issue in CMOS LSI systems, because power supply noise induces logic instability and electromagnetic radiation. Therefore, chip-package-board co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation. Anti-resonance peak can be suppressed by adding on-die capacitance and on-die resistance in chip PDN.
In this paper, effects of critical damping condition for the total PDN impedance has been studied by designing three test chips with different PDN properties. The measured anti-resonance peak in the critical damping condition showed the effective way to suppress the near magnetic field and power supply noises on the chip.
Keyword (in Japanese) (See Japanese page) 
(in English) Power integrity / Chip-package-board co-design / Critical damping condition / Damping factor / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 323, ICD2013-86, pp. 7-12, Nov. 2013.
Paper # ICD2013-86 
Date of Issue 2013-11-20 (CPM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPM2013-109 ICD2013-86 Link to ES Tech. Rep. Archives: CPM2013-109 ICD2013-86

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Co-design for reducing power supply noises with On-die PDN Impedance 
Sub Title (in English)  
Keyword(1) Power integrity  
Keyword(2) Chip-package-board co-design  
Keyword(3) Critical damping condition  
Keyword(4) Damping factor  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Ryota Kobayashi  
1st Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. of Tech.)
2nd Author's Name Hiroki Otsuka  
2nd Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. of Tech.)
3rd Author's Name Genki Kubo  
3rd Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. of Tech.)
4th Author's Name Sho Kiyoshige  
4th Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. of Tech.)
5th Author's Name Wataru Ichimura  
5th Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. of Tech.)
6th Author's Name Masahiro Terasaki  
6th Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. of Tech.)
7th Author's Name Toshio Sudo  
7th Author's Affiliation Shibaura Institute of Technology (Shibaura Inst. of Tech.)
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2013-11-27 09:15:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # CPM2013-109, ICD2013-86 
Volume (vol) vol.113 
Number (no) no.322(CPM), no.323(ICD) 
Page pp.7-12 
#Pages
Date of Issue 2013-11-20 (CPM, ICD) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan