Paper Abstract and Keywords |
Presentation |
2013-11-27 09:15
Co-design for reducing power supply noises with On-die PDN Impedance Ryota Kobayashi, Hiroki Otsuka, Genki Kubo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Toshio Sudo (Shibaura Inst. of Tech.) CPM2013-109 ICD2013-86 Link to ES Tech. Rep. Archives: CPM2013-109 ICD2013-86 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Power integrity is a serious issue in CMOS LSI systems, because power supply noise induces logic instability and electromagnetic radiation. Therefore, chip-package-board co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation. Anti-resonance peak can be suppressed by adding on-die capacitance and on-die resistance in chip PDN.
In this paper, effects of critical damping condition for the total PDN impedance has been studied by designing three test chips with different PDN properties. The measured anti-resonance peak in the critical damping condition showed the effective way to suppress the near magnetic field and power supply noises on the chip. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Power integrity / Chip-package-board co-design / Critical damping condition / Damping factor / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 323, ICD2013-86, pp. 7-12, Nov. 2013. |
Paper # |
ICD2013-86 |
Date of Issue |
2013-11-20 (CPM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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CPM2013-109 ICD2013-86 Link to ES Tech. Rep. Archives: CPM2013-109 ICD2013-86 |
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