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Presentation 2014-01-28 15:00
[Poster Presentation] STT-MRAM Architecture for Improving Throughput
Haruki Mori, Koji Yanagida, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Koji Tsunoda, Toshihiro Sugii (LEAP) ICD2013-110 Link to ES Tech. Rep. Archives: ICD2013-110
Abstract (in Japanese) (See Japanese page) 
(in English) STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory) attracts an attention as the substitute memory of SRAM. The STT-MRAM is a non-volatile memory, and it has the properties of high density, high-speed operation and infinite rewriting. However, the write-operation has limited throughput of memory access because the write operation is slower than read operation, derived from the device characteristics.
In this study, we propose memory architecture of the STT-MRAM for improving the throughput. In the proposed architecture, a 4-Mb STT-MRAM is divided into multiple bunks and conducts parallel writing with a write buffer. The throughput is improved because a next access is carried out by multiple writing before the previous write operation is finished. If a read access to the buffered data occurs, then it can be output from the write buffer immediately.
We designed and implemented the proposed architecture in a 65-nm process.
Keyword (in Japanese) (See Japanese page) 
(in English) STT-MRAM / High-Speed Technique / Cache Memory / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 419, ICD2013-110, pp. 27-27, Jan. 2014.
Paper # ICD2013-110 
Date of Issue 2014-01-21 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2013-110 Link to ES Tech. Rep. Archives: ICD2013-110

Conference Information
Committee ICD  
Conference Date 2014-01-28 - 2014-01-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyoto Univ. Tokeidai Kinenkan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2014-01-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) STT-MRAM Architecture for Improving Throughput 
Sub Title (in English)  
Keyword(1) STT-MRAM  
Keyword(2) High-Speed Technique  
Keyword(3) Cache Memory  
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1st Author's Name Haruki Mori  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Koji Yanagida  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Yohei Umeki  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Shusuke Yoshimoto  
4th Author's Affiliation Kobe University (Kobe Univ.)
5th Author's Name Shintaro Izumi  
5th Author's Affiliation Kobe University (Kobe Univ.)
6th Author's Name Masahiko Yoshimoto  
6th Author's Affiliation Kobe University (Kobe Univ.)
7th Author's Name Hiroshi Kawaguchi  
7th Author's Affiliation Kobe University (Kobe Univ.)
8th Author's Name Koji Tsunoda  
8th Author's Affiliation Low-power Electronics Association & Project (LEAP)
9th Author's Name Toshihiro Sugii  
9th Author's Affiliation Low-power Electronics Association & Project (LEAP)
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Speaker Author-1 
Date Time 2014-01-28 15:00:00 
Presentation Time 120 minutes 
Registration for ICD 
Paper # ICD2013-110 
Volume (vol) vol.113 
Number (no) no.419 
Page p.27 
#Pages
Date of Issue 2014-01-21 (ICD) 


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