Paper Abstract and Keywords |
Presentation |
2014-01-28 15:00
[Poster Presentation]
STT-MRAM Architecture for Improving Throughput Haruki Mori, Koji Yanagida, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Koji Tsunoda, Toshihiro Sugii (LEAP) ICD2013-110 Link to ES Tech. Rep. Archives: ICD2013-110 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory) attracts an attention as the substitute memory of SRAM. The STT-MRAM is a non-volatile memory, and it has the properties of high density, high-speed operation and infinite rewriting. However, the write-operation has limited throughput of memory access because the write operation is slower than read operation, derived from the device characteristics.
In this study, we propose memory architecture of the STT-MRAM for improving the throughput. In the proposed architecture, a 4-Mb STT-MRAM is divided into multiple bunks and conducts parallel writing with a write buffer. The throughput is improved because a next access is carried out by multiple writing before the previous write operation is finished. If a read access to the buffered data occurs, then it can be output from the write buffer immediately.
We designed and implemented the proposed architecture in a 65-nm process. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
STT-MRAM / High-Speed Technique / Cache Memory / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 419, ICD2013-110, pp. 27-27, Jan. 2014. |
Paper # |
ICD2013-110 |
Date of Issue |
2014-01-21 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2013-110 Link to ES Tech. Rep. Archives: ICD2013-110 |
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