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| Presentation | 2014-03-04 16:35 [Memorial Lecture] HIE-Block Latency Insertion Method for Fast Transient Simulation of Nonuniform Multiconductor Transmission Lines Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.)  VLD2013-155 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper describes a hybrid implicit-explicit block latency insertion method (HIE-block-LIM) for fast simulation of nonuniform multiconductor transmission lines. In the HIE-block-LIM, an implicit difference method is used with respect to the current variables in one direction, and an explicit method is adopted to update the other variables. The HIE-block-LIM can alleviate a time step size limitation of the existing block-LIM by taking both advantages of the explicit and implicit difference methods. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | block latency insertion method / fast simulation / hybrid implicit-explicit / nonuniform multiconductor transmission lines / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 454, VLD2013-155, pp. 115-118, March 2014. | |
| Paper # | VLD2013-155 | |
| Date of Issue | 2014-02-24 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2013-155 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2014-03-03 - 2014-03-05 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | HIE-Block Latency Insertion Method for Fast Transient Simulation of Nonuniform Multiconductor Transmission Lines |
| Sub Title (in English) | |
| Keyword(1) | block latency insertion method |
| Keyword(2) | fast simulation |
| Keyword(3) | hybrid implicit-explicit |
| Keyword(4) | nonuniform multiconductor transmission lines |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Takahiro Takasaki |
| 1st Author's Affiliation | Shizuoka University (Shizuoka Univ.) |
| 2nd Author's Name | Tadatoshi Sekine |
| 2nd Author's Affiliation | Shizuoka University (Shizuoka Univ.) |
| 3rd Author's Name | Hideki Asai |
| 3rd Author's Affiliation | Shizuoka University (Shizuoka Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-03-04 16:35:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2013-155 |
| Volume (vol) | vol.113 |
| Number (no) | no.454 |
| Page | pp.115-118 |
| #Pages | 4 |
| Date of Issue | 2014-02-24 (VLD) |
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