Paper Abstract and Keywords |
Presentation |
2014-03-05 10:25
Evaluation of Multiple Cell Upsets Considering Parasitic Bipolar Effects Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) VLD2013-157 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
As a result of the process scaling, radiation-induced Multiple Cell
Upsets (MCUs) become major issue for LSI reliability since it can flip
two or more stored values on storage cells simultaneously.
In this paper, we evaluate MCU rates on flip-flops from circuit-level
simulation which is considering parasitic bipolar effects.
For preparing the parasitic bipolar effect, the p-well structure is
modeled by well-resistance meshes and junction capacitances between
p-well and n-well.
Simulation results show that MCU rates on 65-nm flip-flops are
exponentially reduced according to the distance between flip-flops. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
soft error / multiple cell upset / bipolar effects / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 454, VLD2013-157, pp. 125-130, March 2014. |
Paper # |
VLD2013-157 |
Date of Issue |
2014-02-24 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2013-157 |
Conference Information |
Committee |
VLD |
Conference Date |
2014-03-03 - 2014-03-05 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon |
Paper Information |
Registration To |
VLD |
Conference Code |
2014-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Evaluation of Multiple Cell Upsets Considering Parasitic Bipolar Effects |
Sub Title (in English) |
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Keyword(1) |
soft error |
Keyword(2) |
multiple cell upset |
Keyword(3) |
bipolar effects |
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1st Author's Name |
Jun Furuta |
1st Author's Affiliation |
Kyoto University (Kyoto Univ.) |
2nd Author's Name |
Kazutoshi Kobayashi |
2nd Author's Affiliation |
Kyoto Institute of Technology (Kyoto Inst. of Tech.) |
3rd Author's Name |
Hidetoshi Onodera |
3rd Author's Affiliation |
Kyoto University (Kyoto Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-03-05 10:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2013-157 |
Volume (vol) |
vol.113 |
Number (no) |
no.454 |
Page |
pp.125-130 |
#Pages |
6 |
Date of Issue |
2014-02-24 (VLD) |
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