Paper Abstract and Keywords |
Presentation |
2014-06-12 11:15
Three-dimensional FPGA Structure using High-speed Serial Communication Takuya Kajiwara, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-7 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The three-dimensional (3D) integrated circuit technology is expected to continually improve the LSI (Large Scale Integration) performance when the process miniaturization closing to the physical limitation. How-ever, because the TSV (Through Silicon Via) that used to make the inter-layer vertical connection has much larger area than the transistor, there is a tradeoff between the connectivity and the area overhead. Especially the FPGA (Field Programmable Gate Array) requires large amount of routing resources, it is unrealistic to make the same number of connections vertically as horizontal connections. We have proposed a two-layer compact 3D FPGA with the face-down integration (the base FPGA) method in a previous research. In this paper, we stack multiple base FPGAs with the face-up method, and propose inter-layer high-speed communications with TSV serial connections. The proposed architecture improves FPGA performance by using only few TSVs. The evaluation results show that the proposed 3D FPGA reduces 60% area at the maximum when compared with a 2D FPGA. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
3D-FPGA / High speed serial communication / TSV / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 75, RECONF2014-7, pp. 31-36, June 2014. |
Paper # |
RECONF2014-7 |
Date of Issue |
2014-06-04 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2014-7 |
Conference Information |
Committee |
RECONF |
Conference Date |
2014-06-11 - 2014-06-12 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Katahira Sakura Hall |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2014-06-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Three-dimensional FPGA Structure using High-speed Serial Communication |
Sub Title (in English) |
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Keyword(1) |
3D-FPGA |
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High speed serial communication |
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TSV |
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1st Author's Name |
Takuya Kajiwara |
1st Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
2nd Author's Name |
Motoki Amagasaki |
2nd Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
3rd Author's Name |
Masahiro Iida |
3rd Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
4th Author's Name |
Morihiro Kuga |
4th Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
5th Author's Name |
Toshinori Sueyoshi |
5th Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-06-12 11:15:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2014-7 |
Volume (vol) |
vol.114 |
Number (no) |
no.75 |
Page |
pp.31-36 |
#Pages |
6 |
Date of Issue |
2014-06-04 (RECONF) |
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