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| Presentation | 2014-07-03 11:05 Implementation of FPGA Section for Anomaly Detection Acceleration by HW/SW Cooperation Shun Yanase, Hajime Shimada, Yukiko Yamaguchi, Hiroki Takakura (Nagoya Univ.)  ISEC2014-16 SITE2014-11 ICSS2014-20 EMM2014-16 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Anomaly-based Intrusion Detection System (anomaly IDS) is an approach of the IDS which creates a discrimination circuit from normal traffic and detects malicious traffic by grading deviant traffic with the discrimination circuit. In recent years, because of the spread of the Internet usage and network clients, the network traffic is becoming huge amount. So we are afraid that the anomaly IDS often fails capturing network packet because of deficiency of a performance when it monitors an internal network of a large-scale organization. To solve this problem, we propose HW/SW corporation anomaly detection system using FPGA to achieve real-time anomaly detection processing on high-traffic network. We adopt PAYL algorithm as a suitable one for hardware algorithm which applies 1-gram method to network packet payload and calculate maharanobis distance between training data to detect malicious traffic. We implemented Features Extraction module which is estimated as a bottleneck of the PAYL algorithm into FPGA. The result shows that an estimated throughput of the system becomes 5.155Gbps which is 10.72 times larger value in case of SW only implementation. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Intrusion detection system / Anomaly Detection / FPGA / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 117, ICSS2014-20, pp. 75-80, July 2014. | |
| Paper # | ICSS2014-20 | |
| Date of Issue | 2014-06-26 (ISEC, SITE, ICSS, EMM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ISEC2014-16 SITE2014-11 ICSS2014-20 EMM2014-16 |
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| Conference Information | |
| Committee | ICSS ISEC SITE EMM IPSJ-CSEC IPSJ-SPT |
| Conference Date | 2014-07-03 - 2014-07-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | San-Refure Hakodate |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Security |
| Paper Information | |
| Registration To | ICSS |
| Conference Code | 2014-07-ICSS-ISEC-SITE-EMM-CSEC-SPT |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of FPGA Section for Anomaly Detection Acceleration by HW/SW Cooperation |
| Sub Title (in English) | |
| Keyword(1) | Intrusion detection system |
| Keyword(2) | Anomaly Detection |
| Keyword(3) | FPGA |
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| 1st Author's Name | Shun Yanase |
| 1st Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 2nd Author's Name | Hajime Shimada |
| 2nd Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 3rd Author's Name | Yukiko Yamaguchi |
| 3rd Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 4th Author's Name | Hiroki Takakura |
| 4th Author's Affiliation | Nagoya University (Nagoya Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-07-03 11:05:00 |
| Presentation Time | 25 minutes |
| Registration for | ICSS |
| Paper # | ISEC2014-16, SITE2014-11, ICSS2014-20, EMM2014-16 |
| Volume (vol) | vol.114 |
| Number (no) | no.115(ISEC), no.116(SITE), no.117(ICSS), no.118(EMM) |
| Page | pp.75-80 |
| #Pages | 6 |
| Date of Issue | 2014-06-26 (ISEC, SITE, ICSS, EMM) |
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