Paper Abstract and Keywords |
Presentation |
2014-08-05 10:25
Development of a Low Standby Power, Six-Transistor CMOS SRAM Employing a Single Power Supply Ryusuke Ito (Chuo Univ.), Nobuaki Kobayashi (NUT), Tadayoshi Enomoto (Chuo Univ.) SDM2014-73 ICD2014-42 Link to ES Tech. Rep. Archives: SDM2014-73 ICD2014-42 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, not only to expand both “write” and “read” stabilities, but also to achieve a low standby power dissipation (PST) and a high static-noise margin in a single power supply, 90-nm, 2-kbit, six-transistor CMOS SRAM. The SVL circuit can adaptively lower and higher a word-line voltage for “read” and “write” operations, respectively. It can also adaptively lower and higher a memory cell supply voltage for “write” and “hold” operations, and the “read” operation, respectively. The PST of the developed SRAM is only 0.984 μW, namely, 9.57% of that (10.28 µW) of the conventional SRAM at a supply voltage (VDD) of 1.0 V. A static-noise margin of the developed SRAM is 0.1839 V and that of the conventional SRAM is 0.343 V at VDD of 1.0 V. A Si area overhead of the SVL circuit is only 1.383 % of the conventional SRAM. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOS / SRAM / static-noise margin / standby power dissipation / leakage current / Self-controllable Voltage Level (SVL) circuit / area overhead / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 175, ICD2014-42, pp. 59-64, Aug. 2014. |
Paper # |
ICD2014-42 |
Date of Issue |
2014-07-28 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2014-73 ICD2014-42 Link to ES Tech. Rep. Archives: SDM2014-73 ICD2014-42 |
Conference Information |
Committee |
ICD SDM |
Conference Date |
2014-08-04 - 2014-08-05 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hokkaido Univ., Multimedia Education Bldg. |
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(See Japanese page) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2014-08-ICD-SDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Development of a Low Standby Power, Six-Transistor CMOS SRAM Employing a Single Power Supply |
Sub Title (in English) |
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Keyword(1) |
CMOS |
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SRAM |
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static-noise margin |
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standby power dissipation |
Keyword(5) |
leakage current |
Keyword(6) |
Self-controllable Voltage Level (SVL) circuit |
Keyword(7) |
area overhead |
Keyword(8) |
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1st Author's Name |
Ryusuke Ito |
1st Author's Affiliation |
Chuo University (Chuo Univ.) |
2nd Author's Name |
Nobuaki Kobayashi |
2nd Author's Affiliation |
Nagaoka University of Technology (NUT) |
3rd Author's Name |
Tadayoshi Enomoto |
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Chuo University (Chuo Univ.) |
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Speaker |
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Date Time |
2014-08-05 10:25:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
SDM2014-73, ICD2014-42 |
Volume (vol) |
vol.114 |
Number (no) |
no.174(SDM), no.175(ICD) |
Page |
pp.59-64 |
#Pages |
6 |
Date of Issue |
2014-07-28 (SDM, ICD) |
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