Paper Abstract and Keywords |
Presentation |
2014-11-26 16:15
General-Purpose Pattern Recognition Processor Based on the k Nearest-Neighbor Algorithm with High-Speed, Low-Power Shogo Yamasaki, Toshinobu Akazawa, Fengwei An, Hans Juergen Mattausch (Hiroshima Univ.) VLD2014-75 DC2014-29 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A learning and pattern recognition processors for the k nearest neighbor (k-NN) recognition algorithm using a nearest Euclidean-distance search associative memory and a classification circuit for the k nearest neighbors. A SoC design example of the complete k-NN system is implemented in 180nm CMOS with 32 reference vectors and 2~8 classes. Small silicon area of 3.51 mm2, low power consumption of 5.02mW and a maximum operating frequency of 42.9MHz (at Vdd=1.8V) are achieved, Compared to implementation in software, the chip operates with a factor 1000 better energy efficiency.
Keywords associative memory, Euclidean distance, k-NN, pattern matching, pattern recognition |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
associative memory / Euclidean distance / k-NN / pattern matching / pattern recognition / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 328, VLD2014-75, pp. 21-26, Nov. 2014. |
Paper # |
VLD2014-75 |
Date of Issue |
2014-11-19 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2014-75 DC2014-29 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2014-11-26 - 2014-11-28 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
B-ConPlaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2014 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
General-Purpose Pattern Recognition Processor Based on the k Nearest-Neighbor Algorithm with High-Speed, Low-Power |
Sub Title (in English) |
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Keyword(1) |
associative memory |
Keyword(2) |
Euclidean distance |
Keyword(3) |
k-NN |
Keyword(4) |
pattern matching |
Keyword(5) |
pattern recognition |
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1st Author's Name |
Shogo Yamasaki |
1st Author's Affiliation |
Hiroshima University (Hiroshima Univ.) |
2nd Author's Name |
Toshinobu Akazawa |
2nd Author's Affiliation |
Hiroshima University (Hiroshima Univ.) |
3rd Author's Name |
Fengwei An |
3rd Author's Affiliation |
Hiroshima University (Hiroshima Univ.) |
4th Author's Name |
Hans Juergen Mattausch |
4th Author's Affiliation |
Hiroshima University (Hiroshima Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-11-26 16:15:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2014-75, DC2014-29 |
Volume (vol) |
vol.114 |
Number (no) |
no.328(VLD), no.329(DC) |
Page |
pp.21-26 |
#Pages |
6 |
Date of Issue |
2014-11-19 (VLD, DC) |
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